Abstract: A system and method for transmission control protocol (TCP) acceleration. Incoming acknowledgement (ACK) packets belonging to a TCP session are received, and an upstream queue is searched for queued acknowledgment packets belonging to the same TCP session. If the incoming acknowledgment packet is not a duplicate of the queued acknowledgment packet, one of the queued acknowledgment packets is replaced with the incoming acknowledgment packet in the position in the upstream queue occupied by the oldest of the queued acknowledgment packets. After the oldest queued acknowledgement packet is replaced, remaining acknowledgement packets in the queue are dropped.

Abstract: A method for estimating an SNR-related parameter, such as ES/N0, from one or more symbols. The number of symbols within a predetermined number of symbols that fall within one or more collection areas is counted. The count is then associated with a value of the SNR-related parameter. This association may be performed through one or more lookup tables. In one application, a scaling factor is derived from the count. The scaling factor may be used to scale symbols before they are quantized and inputted into a trellis decoder such as a log-MAP decoder.

Abstract: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A correctly decoded CRC block, indicating a decoded segment is correct with a high degree of certainty, assigns a very high confidence level to the bits in this segment and is fed back to inner and/or outer decoders (with interleaving, when appropriate) for improved iterative decoding. High confidence bits may be scattered throughout inner decoded frames to influence other bit decisions in subsequent iterations. Turbo decoders typically operate relatively well at regions where the BER is high; the invention improves iterative decoder operation at lower BERs, lowering the ‘BER floor’ that is sometimes problematic with conventional turbo decoders.

Abstract: A DLL comprises detection circuitry configured to detect a too_slow and a too_fast operating state and correction circuitry configured to correct operation of the DLL when a too_fast or too_slow state is detected. The correction circuitry can be configured to swallow a pulse of the input clock signal when a too_fast condition is detected. The correction circuitry can also be configured to force the DLL into a too_fast operation state, when a too_slow operation state is detected. The correction circuitry can then also be configured to swallow a pulse of the input clock signal once the DLL is in the too_fast operation state.

Abstract: An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to implement quadrature phase error correction, and a feedback system or compensation engine used to process the sensed error voltage and apply a corresponding correction signal to the adjustable phase delay.

Abstract: A method and apparatus implements a Virtual Exchange Reference Impact (VERI) technique to define a pattern to shape the spectrum of a cabinet deployed system to minimize its impact, e.g., FEXT, into an exchange deployed system while achieving effective cabinet system performance, e.g., in terms of data transmission rate. The invention shapes the cabinet system to replicate a self-impact of the exchange system on itself based on the known distance of the cabinet from the exchange. The shaping is required when both exchange and cabinet systems share the same bundle and exhibit overlapped bandwidths. A particular example consists of VDSL deployed from remote cabinet impacting ADSL2/ADSL2+ deployed from the exchange.

Abstract: Embodiments of sleep mode systems and methods are disclosed. In one method embodiment, among others, a sleep mode method comprises commencing a sleep mode, and during the sleep mode, queuing a plurality of frames for a burst transmission.

Abstract: A 10 MHz channelized orthogonal frequency division multiplexing (OFDM) transmitter is provided that communicates using a modified OFDM packet structure with a half-rate oscillator having standard accuracy. The transmitter has an inverse fast fourier transform (IFFT) data processor that appends an outer pair of data subcarriers on either end of an OFDM subcarrier profile. An IFFT long sync processor appends an outer pair of binary phase shift key (BPSK) subcarriers on either end of an OFDM long sync subcarrier profile. By copying or appending the information of the data subcarriers closest to zero Hz. to more robust locations, 10 MHz channelized OFDM can be achieved with half-rate clocks and 20 PPM oscillators.

Abstract: A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the microprocessor within the personal computer to pre-compute the time critical PHY waveforms required to respond to received packets. For instance, the acknowledge (ACK) waveform required to respond to a received WLAN packet is pre-computed and stored in the PC memory. Upon receipt of a valid packet, the samples of the ACK waveform are transferred from the PC memory to a digital to analog converter (DAC). The DAC generates the transmit waveform required for the radio modulator. By pre-computing the transmit waveform samples, the required loading on the PC microprocessor is reduced during time critical periods.

Abstract: An image processing system that performs edge-enhancement on an image. The image processing system processes a region of the image at a given time. One specific pixel of an image region is compared to several surrounding pixels to determine the existence of a black edge or a white edge in the image. Additionally, the image processing system includes a classifier that determines whether the image is substantially text-like or substantially photo-like. When the image is substantially text-like, a dynamic black threshold is used to determine the existence of a black edge within the image. The dynamic black threshold is modified during the processing of the image by the image processing system as a function of the relationship between the one specific pixel to at least one other of the several surrounding pixels. The image processing system selectively applies a first threshold scheme or a second threshold scheme upon identification to the image depending on the characteristics of the one specific pixel.

Abstract: Embodiments of systems, methods, and computer program products may facilitate translation of machine code associated with a first processor for execution on a second processor. Machine code associated with a first processor may be translated into a translated program that includes one or more translation instructions for execution on the second processor. The one or more translation instructions are used exclusively to translate machine code that is associated with a processor other than the second processor. The translated program may be stored in a storage medium where it may be executed using the second processor. Each translation instruction that involves access of the storage medium may be dispatched to one or more translation load-store units that are dedicated exclusively to processing the translation instructions.

Abstract: A method for actively detecting link failures on a high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. A probe packet is sent, and a probing timer is set whenever either a specified number of bad packets are received, or an idle timer expires. If a response to the probe packet is received before the probe timer expires then the link is deemed valid, otherwise the link is presumed to have failed. Preferably, either the node boards or the switch fabric boards are configured to properly handle a probe pack, which preferably has identical source and destination addresses.

Abstract: One method for analyzing a bitstream having a plurality of compressed pictures comprises computing an initial arrival time and a final arrival time of a compressed picture, wherein the initial arrival time is equal to an earlier of the final arrival time of the immediately previous compressed picture or equal to a sum of a fixed time plus a sum of removal delays of all of the compressed pictures between the first compressed picture following the buffering period message and the compressed picture, including the compressed picture, and wherein the final arrival time is equal a sum of the initial arrival time and a time calculated based on the number of bits associated with the compressed picture at the bit rate; and verifying that a difference between the final removal time and the initial arrival time does not exceed the time for reaching the buffer size at the bit rate.

Abstract: Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a macroblock decode module configured to decode a plurality of context adaptive binary arithmetic coding (CABAC) encoded symbols corresponding to a slice without processor intervention.

Abstract: A system and method for a bit-loading algorithm based on an equal error rate principle for each sub-channel (bin) used in a discrete multi-tone modulation (DMT) system. The system and method of the present invention provides a bit-loading algorithm that provides long reach, high data rate and good error performance at a given condition. The bit-loading method and system depends on the Shannon channel capacity formula to allocate bits to different sub-channels. For DMT, the system and method tabulates different SNR GAP for different sub-channels (bins), and constructs a look-up table for the SNR GAP with different bits to achieve a better performance for the DMT system.

Abstract: A method and apparatus for processing demodulated data comprising received symbol data is disclosed. A decoder is used to compute estimated symbols and corresponding reliability metrics. The reliability metrics are transformed into reliability weights. Optionally, residuals relating to the difference between the received symbol data and the estimated symbols are computed. Output data are generated comprising any combination of the following: estimated symbols, reliability weights, residuals, and received symbol data. The residuals may be weighted by the reliability metrics and used by demodulation or error compensation loops to instantaneously reduce or increase the bandwidth of these loops.

Abstract: Provided are decoding methods and decoders for separating luminance and chrominance components of a video signal. In one aspect, a reference subcarrier of a first line of the video signal is used for subsequent lines by applying an appropriate rotation to the reference subcarrier of the first line for each subsequent line. In another aspect, comb filtering is adaptively controlled based on determining whether 90 or 180 degrees relationship is maintained from line to line. In a further aspect, both complimentary and non-complimentary comb filtering are implemented. In yet another aspect, SECAM bell filtering is achieved by rotating the video signal to obtain a baseband signal, low-pass filtering and modulating the baseband signal, and subtracting the modulated low-pass filtered baseband signal from the video signal to notch the chroma component from the luma component.

Abstract: Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a macroblock decode module configured to decode a plurality of context adaptive binary arithmetic coding (CABAC) encoded symbols corresponding to a slice without processor intervention.

Abstract: Systems and methods for multi-stage signal detection in MIMO transmission including Bernoulli-Gaussian detection are provided. A multistage iterative signal decoder is provided that exploits the property that in a relatively simply decoding scheme such as mean square error (MSE) or zero-forcing (ZF) only a small portion of the total symbols are mis-detected. Therefore, an optimality test is performed on the output of a relatively low complexity decoder unit. If the symbol passes the optimality test, it is presumed to be correctly decoded. Otherwise, the symbol is sent for further processing to a relatively higher complexity decoding unit such as a sphere decoder. In this way, processing efficiency is increased, because only those symbols requiring additional processing are processed by the high complexity processing unit.

Abstract: A line card for use in a node of a network to connect to optical network lines is provided. The line card includes an optical interface, and a serializer/deserializer (SERDES) operating at a first frequency. The line card also includes a framer operating at a second frequency where the first frequency is higher than the second frequency. The framer includes a digital step up converter to receive data from the SERDES and a digital step down converter to supply data to the SERDES. The step down converter includes a set of input buffers where each input buffer receives a word of nibbles from the framer. The input buffers are loaded one after another, but extraction from each of the input buffers to a multi-stage multiplexer is triggered so long as a non-reset window is preserved. The step up converter includes a set of input buffers and a register array where each input buffer receives a word of nibbles from the register array.