Abstract: Systems and methods for connection and remote configuration of wireless nodes communicating on a shared-communications channel. A master node includes a processor configured to generate a frame including configuration information designating network configuration parameters for configuring a remote wireless node for network communications. The master node transmits the frame over the shared communication channel to a slave node to be configured. The slave node includes a receiver for receiving the frame from the master node on the shared communication channel. The slave node includes a processor for configuring the wireless node to communicate according to the network configuration parameters designated by the configuration information in the frame.

Abstract: An interface between radios supporting different air interfaces is disclosed that avoids some of the costs and disadvantages associated with inter-radio interfaces in the prior art. The present invention enables the needed coordination across multiple wireless protocols, such as 802.11 and Bluetooth, by providing a communication link spanning different integrated circuits when each radio is on a separate integrated circuit. This low cost, low complexity link can be added to standard integrated circuits produced by individual companies without adding appreciably to the overall cost of the integrated circuits.

Abstract: Systems and methods for enabling wireless devices to discover a number of other proximate wireless devices are disclosed. The discovery may include the discovery of network configuration parameters useful for establishing a connection between the wireless devices. The disclosed systems and methods for device discovery may operate in a number of different modes to timely discover wireless devices that receive communications continuously, as well as wireless devices that turn off their wireless receivers for intermittent periods of time. The wireless devices may, for example, communicate using the IEEE 802.11 protocol.

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.

Abstract: A method and apparatus implements a Virtual Exchange Reference Impact (VERI) technique to define a pattern to shape the spectrum of a cabinet deployed system to minimize its impact, e.g., FEXT, into an exchange deployed system while achieving effective cabinet system performance, e.g., in terms of data transmission rate. The invention shapes the cabinet system to replicate a self-impact of the exchange system on itself based on the known distance of the cabinet from the exchange. The shaping is required when both exchange and cabinet systems share the same bundle and exhibit overlapped bandwidths. A particular example consists of VDSL deployed from remote cabinet impacting ADSL2/ADSL2+ deployed from the exchange.

Abstract: An equalizer is trained based on a packet, which includes a preamble segment, a header segment and a payload segment, wherein each of the segments has a symbol rate. Further, the equalizer has a number of filter taps. A training method of the equalizer includes adapting the filter taps according to the preamble segment and extracting from the header segment a symbol rate value of the payload segment. If the symbol rate value of the payload segment, which is extracted from the header segment, indicates that such symbol rate is higher than the symbol rates of the preamble and header segments, the filter taps are re-adapted according to the preamble segment, and a number of zeros are inserted into the preamble and header segments to account for the difference between the symbol rate of the payload segment and the symbol rates of the preamble and header segments.

Abstract: A system and method for wireless waking computing devices over a computer network is provided. A signal is broadcast over the network that includes one or more device specific wake-up data sequences. Each device specific wake-up data sequence includes multiple iterations of the hardware address of the wireless network card associated with that device. While in a reduced power or “sleep mode”, the wireless network card monitors wireless channels for packets containing a wake-up data sequence. If a wake-up data sequence is received, the sequence is matched against the hardware address information for that network card. If a match is determined, the network card sends a signal to the computing device causing full system power to be restored. A signal is sent to the network confirming that the device has been successfully woken from the sleep mode.

Abstract: A communications system includes an internet protocol network, a calling modem and an answering modem configured to effectively handle network latency. The calling modem includes a timer storing a network latency value. The network latency value is compared to a network latency threshold. If the network latency threshold is less than the network latency value, then a high speed modem connection is continued. If the network latency value is greater than the network latency threshold, then the high speed modem connection is terminated. In place of the high speed modem connection, a low speed modem connection is established. The calling modem is operable to transmit a modem connection selection signal for selecting a high speed modem connection or a low speed modem connection. The answering modem is operable to receive the modem connection selection signal.

Abstract: Method and System for evaluating a turbo-coding scheme suitable for VDSL2 systems. The scheme is a Turbo-Trellis Coded Modulation TTCM that makes use of a Parallel Concatenated Convolutional Code (PCCC) including an inner Latin square/rectangular matrix of Random sequence pattern Interleaver (LRI) of approximately 2044 bits. In the presence of the outer Reed Solomon Code but without an outer interleaver (fast mode), the method and system provides 7.1 dB of average net coding gain, i.e., 2.6 dB of coding gain improvement relative to the standard 16 states 4-dimensional (4-D) trellis code used in current ADSL2 systems. The substantial coding gain achieved through the method and system, leads to an increase in the VDSL2 rate by 38% at 6 kft against local exchange carriers, such as ILEC (SBC) conditions with approximately 1.5 ms of latency. By encoding only two bits per tone (i.e., 1 bit per dimension), the turbo code implementation complexity is kept reasonable.

Abstract: Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.

Abstract: A method and apparatus for scheduling upstream data packets in a communication system is described. The present inventive method obtains a priority value (PV) for an upstream data packet and compares (using hardware registers) the PV of a queued upstream data packet to a current system timer. In accordance with one embodiment of the present invention, the current system timer comprises the current clock time of the communication system. When a PV equals the current system timer, the method transmits the upstream data packet associated with the PV to the CMTS via the upstream transmission path.

Abstract: A circuit board capacitor structure operable as a high voltage isolation barrier in communication circuitry. Capacitor electrodes form a capacitive structure directly on a printed circuit board's opposing sides. The PCB substrate intermediate the electrodes functions as the capacitive structure's dielectric material. The capacitor electrodes are sized such that the electrodes' area and the substrate's dielectric properties create the desired capacitance. Alternatively, a multi-layered PCB may be utilized where layer(s) is/are used to form the capacitive structure. The circuit board capacitor may couple communication circuitry located on the PCB's various sides. The circuit board capacitor operates as a high voltage isolation barrier in data access arrangements, separating line and system side circuitry. Further, the high voltage isolation barrier may include multiple circuit board capacitors to realize differential communications and/or multiple datapaths.

Abstract: A multi-mode device, capable of channel equalization and packet collision detection, includes a first switch, which is capable of receiving a transmit signal and a receive signal and outputting a filter input, which is multiplied by a first filter tap to generate a first product. The device also includes a delay unit for receiving the filter input and generating a delayed filter input, wherein the delayed filter input is multiplied by a second filter tap to generate a second product; an adder for adding the first product with the second product and generating a filter output; a decision block, which receives the filter output and generates a decision output; and a second switch capable of receiving the decision output, a training sequence and the receive signal and outputting a second switch output. The device generates an error signal using the filter output and the second switch output.

Abstract: Systems and methods for multi-stage signal detection in MIMO transmission including Bernoulli-Gaussian detection are provided. A multistage iterative signal decoder is provided that exploits the property that in a relatively simply decoding scheme such as mean square error (MSE) or zero-forcing (ZF) only a small portion of the total symbols are mis-detected. Therefore, an optimality test is performed on the output of a relatively low complexity decoder unit. If the symbol passes the optimality test, it is presumed to be correctly decoded. Otherwise, the symbol is sent for further processing to a relatively higher complexity decoding unit such as a sphere decoder. In this way, processing efficiency is increased, because only those symbols requiring additional processing are processed by the high complexity processing unit.

Abstract: A communication device such as a cable modem that has a first interface for receiving data from a cable media, and a pattern matching engine that evaluates patterns in the data that is received at the first interface of the cable modem and that enables the determination of appropriate procedures for treatment of the data. The pattern matching engine of the cable modem may be configured to match address segments of the data that is received at the first interface of the cable modem. In addition, the pattern matching engine is often a programmable pattern matching engine that may be programmed according to patterns that are desired to matched during various operations of the cable modem. Of note, the pattern matching engine enables pattern matching of various length frame portions. Various aspects of the present invention may also be found in a method for a communication device to compare a predetermined pattern to a pattern that corresponds to a portion of a data frame.

Abstract: According to an embodiment, a DC driver circuit is coupled to a tip/ring line. The DC driver circuit includes a first capacitor coupled to a first switch where the first switch is coupled to an amplification circuit. An RC circuit is coupled to a second switch where the second switch is coupled to the amplification circuit. During a make state, the first and second switches are closed, causing the amplification circuit to draw current from the tip/ring line. During a break state, the first and second switches are open, preventing the amplification circuit from drawing current from the tip/ring line. The transition from the make state, during which a significant amount of current is drawn from the tip/ring line, to the break state, during which no current should be drawn from the tip/ring line, occurs at a rate that results in a significantly reduced voltage peak at the tip/ring line.

Abstract: A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.

Abstract: The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path.

Abstract: Multiple ICs communicate with a controller through a shared bus. The ICs are also joined to an output of the controller in a daisy chain configuration. Each IC includes an input for receiving a signal on a link of the daisy chain and an output for providing a signal on a link of the daisy chain. The daisy chain links are used for address initialization. Thus only one controller pin and two IC pins are required for address initialization. The daisy chain links may be used for distributing address data, or may be used for distributing an enable signal that allows an IC to store address data provided on the shared bus.