Abstract: A home network controller provides a user-visible indication of the integrity of a physical connection to a home network. The home network controller periodically checks an interrupt status register for receipt of a physical-layer packet. Receipt of a physical-layer packet serves as a proxy for a functional physical connection, and non-receipt of a packet serves as a proxy for a non-functional physical connection. To avoid race conditions, the controller will indicate failure of a previously functional physical connection if no packet was received during the period but a packet was transmitted during the period and a packet was transmitted during the immediately previous period. A heartbeat signal avoids deadlocks by transmitting a packet if the interrupt status register indicates no packets were received or transmitted during the period.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.

Abstract: A method and apparatus that identifies the degree of correlation between a demodulated in-phase (I) and quadrature (Q) signal that represents phase imbalance between the in-phase (I) and quadrature (Q) signal and corrects the imbalance.

Abstract: A packet communication scheduling system comprises tunnel schedulers, a packet scheduler, and a rate controller. The packet scheduler generates a packet schedule and first-set information in response to packet information. The first tunnel scheduler generates a first schedule for a first set of tunnels in response to the first-set information. The first tunnel scheduler also generates second-set information in response to the first-set information. The second tunnel scheduler generates a second schedule for a second set of tunnels in response to the second-set information. The second tunnel scheduler also generates third-set information in response to the second-set information. The third tunnel scheduler generates a third schedule for a third set of tunnels in response to the third-set information. The third tunnel scheduler selects a next third-set tunnel identifier based on the third schedule.

Abstract: Packet-Based Direct Memory Access. The present invention overcomes the oftentimes hardware consumptive and complex implementation of conventional direct memory access (DMA) that employs descriptors. The descriptors that must are employed by conventional DMA must be set up by software, and the handshaking between the hardware and software is typically very cumbersome. The packet-based DMA performed in accordance with the present invention is operable and adaptable to various types of cell-based DMA modes. A flow control regulator, or flow control state machine, is used to control the packet-based DMA performed in accordance with the present invention. Two different multiplexors (MUXs) are employed, one for each of the transmit and the receive packet-based DMA transfers, to select the various cases of packet-based DMA. The present invention is operable within various modes including asynchronous transfer mode (ATM) cell-based asynchronous digital subscriber loop (ADSL) applications.

Abstract: A signal processor that contains a programmable logic circuitry that is re-configurable in response to various parameters including, but not limited to, characteristics of a plurality of input data that is provided to the signal processor. The signal processor contains, among other things, a programmable logic configuration circuitry that provides a logic configuration to the programmable logic circuitry. In certain embodiments of the invention, the signal processor employs a wide word width to program the programmable logic circuitry, the wide word width is operable to configure an entirety of the programmable logic circuitry. The programmable logic configuration circuitry further contains a default configuration circuitry and an adaptive configuration circuitry. The default configuration circuitry contains a default logic configuration for the programmable logic circuitry.

Abstract: An integrated circuit processes communication packets and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packets. The scheduling circuitry comprises multiple scheduling boards where at least some of the scheduling boards have multiple priority levels. The scheduling circuitry processes the scheduling boards to schedule and subsequently initiate transmission of the communication packets.

Abstract: A system and method are provided for sensing a sound system. In one embodiment, a sound card or other such device is provided that includes an analog audio output system and a digital audio output system. Both the analog and digital audio output systems are coupled to a common audio output port through which either an analog or digital sound system is driven. The common audio output port provides a first line out and a second line out that may be employed to transmit the right and left channels of a stereo analog audio signal. Alternatively, one of the first and second line outs may be employed to transmit a digital audio signal, where the remaining line out is coupled to ground. Only one of the analog and digital output systems are enabled to transmit sound through the common audio output port to the respective sound system at a time. Accordingly, the present system and method are provided to determine whether an analog or digital sound system is coupled to the common audio output port.

Abstract: A receiver circuit is for processing a received signal which includes at least a first portion and a second portion which repeats the content of the first portion after a repeat interval. For example, the receiver may be for DVB-T signals using COFDM. Two correlation values are measured. The first is between the first portion of the received signal, delayed by the repeat interval plus a difference interval, and the second portion. The second is between the first portion of the received signal, delayed by the repeat interval minus a difference interval, and the second portion. Any difference between the correlation values represents a difference between the receiver sampling rate, and the required sampling rate, and can be used to adjust the receiver sampling rate.

Abstract: An integrated circuit processes communication packets and comprises co-processor circuitry and a core processor. The co-processor circuitry is configured to operate in parallel with the core processor. The co-processor circuitry receives and stores the communication packets in data buffers. The co-processor circuitry also determines a prioritized processing order. The core processor executes a packet processing software application that directs the processor to process the communication packets in the data buffers based on the prioritized processing order.

Abstract: Method and apparatus for an improved echo canceller provide for faster convergence in echo canceling, which also contribute to better voice quality and provide for an increase in the capacity (number of channels) of a multi-channel voice processing products. Whitening filters are used to flatten the spectrum of the signals that pass through the echo canceller. Higher convergence rate is achieved when flattened signals pass through the echo canceller. A reconstruction filter is used to introduce the spectral envelop back into the outbound signal.

Abstract: A finite impulse response (FIR) filter employing hybrid coefficients for use in analog-to-digital and digital-to-analog conversion. Clock jitter introduced by the transmission medium may be compensated for by calculating an early interpolated data value and a late interpolated data value for each data point, and using the difference between the early and late interpolated values to produce a correction signal to the slicer clock in the converter. Hardware may be minimized by employing a hybrid coefficient in each filter tab which is reflective of the difference between an early and a late interpolated data value.

Abstract: Adaptive analog equalization. The present invention provides an analog equalization solution that is assured to converge irrespective of the initial conditions of the adaptation. For very high frequency communication applications, including DS3 or E3 line code applications operating at frequencies approaching 45 MHz, the analog adaptive equalization employs double sampling. One of the samples is used to make the decision if a transition actually goes to zero, and the other of the samples is used to drive the adaptation loop to converge. The present invention employs a high pass network and an adaptable gain to control an adaptive analog equalizer structure. There are two different feedback paths to ensure convergence of the present invention. In one embodiment, one feedback path is the gain control feedback path that is provided to the adaptive analog equalizer structure. The other feedback path is provided to a variable gain amplifier.

Abstract: A modem utilizing a DAA having line side circuitry including a telephone network interface and system side circuitry including a host system interface. The line side circuitry and the system side circuitry are separated by a high voltage isolation barrier. In accordance with the invention, the high voltage isolation barrier and other DAA circuitry are configured such that data and control information may be communicated between the system side circuitry and the line side circuitry using a serialized digital communication protocol. In one embodiment of the invention, the line side circuitry of the modem includes detection and measurement circuitry that is programmable to measure or establish electrical characteristics (e.g., tip/ring voltage and loop current) of the telephone line interface connection. Command information for the programmable circuitry is multiplexed with data communicated across the high voltage isolation barrier.

Abstract: An apparatus for carrying electrical data signals and electrical power over a power line is disclosed. The apparatus includes a data processing device, a power supply, and a data signal transceiver. The apparatus also includes an interference filter coupled to the power line and to the power supply and configured to reject electromagnetic interference. A coupling circuit that is electromagnetically coupled to the power line is also disclosed. The coupling circuit is configured to transmit and receive data signals carried through the power line. The coupling circuit is coupled to the data signal transceiver. The data signal transceiver is configured to transmit and receive the data signals to and from the data processing device.

Abstract: In one embodiment, a device includes but is not limited to: a precoder having a precoder input and a precoder output; a spectral shaper, having a spectral-shaper transfer function and being operably coupled internal to said precoder; and a precoder filter, internal to the precoder, the precoder filter having a transfer function which provides substantially the inverse of the spectral-shaper transfer function.

Abstract: An improved EX-CELP or RCELP encoding scheme is proposed, in which, at the encoder side, a speech signal is perceptually weighted signal prior to entering a time scale modification module, then the modified signal is transformed into another domain, such as the speech or LP short-term residual domain, using the corresponding inverse filtering operation directly or possibly combined with another processing, for instance a short-term LP filtering. A shift function is calculated in the time scale modification process to associate the position of each sample in the modified signal with its original position before the modification. The positions of the samples in the modified signal that correspond to sub-frame boundaries of the original signal are evaluated to switch filters for the inverse filtering at the appropriate instants. Therefore, the synchronization between the inverse filters and the modified signal is maintained.

Abstract: A quick startup procedure for a modem system utilizes known characteristics of a previously established communication channel to reduce the initialization period associated with subsequent connections over the same channel. In response to the establishment of a call, the modem devices determine whether the quick connect protocol is supported. If so, then the called modem transmits a modified answer tone to the calling modem. The calling modem analyzes the signal received in response to the modified answer tone to determine whether characteristics of the current channel are similar to stored characteristics associated with a previous connection over the same channel. If a channel “match” is found, then the modem devices carry out a quick initialization routine that eliminates, abbreviates, or modifies a number of procedures or protocols that are carried out in conventional modem startup processes.

Abstract: A fully integrated single-loop frequency synthesizer, which can serve as a local oscillator for a broadband tuner, is disclosed, thus allowing the creation of a single-chip solution for broadband applications. The tank circuits are integrated into the tuner chip through the combination of a phase-locked loop and multiple on-chip VCOs comprising narrow-tuning range varactors. Drift in the VCOs caused by heat is overcome by designing the VCOs to overlap each other. Initial tolerance problems associated with the VCOs are overcome by the use of a calibration method. The calibration of the VCOs is accomplished by utilizing the lock detect output of the phase-locked loop and a binary search algorithm. The edges of each VCO are determined with this calibration method, thereby enabling VCO selection based on the desired channel. A sufficient number of VCOs are provided such that whatever the initial tolerance shift, the full broadband spectrum can still be covered after calibration.

Abstract: A communication session is established between an APCM modem and a DPCM modem. The central office interrupts the communication session by transmitting a call-waiting alert signal to the APCM modem. In response to the alert signal, the APCM modem transmits a caller ID data request to the central office. The APCM modem further transmits an on hold notification to the DPCM modem to prevent the DPCM modem from terminating the communication session as a result of the interruption by the alert signal and/or receipt of the caller ID data by the APCM modem. The DPCM modem is placed on hold while the APCM modem answers the call waiting. Subsequently, the APCM modem initiates a quick connect procedure to re-establish the communication session with the DPCM modem.