Abstract: A telephony system and method for providing telephony services to remote users. The telephony system comprises a user side and a provider side. The user side includes a telephony instrument and a personal computer for establishing communication with the provider side via a communication gateway, a communication device and a wide area network, such as the Internet. The provider side includes a virtual private network in communication with the wide area network and a communication network. The communication network is in communication with a telephony server interfacing with a telephone switched system. The telephone switched network provides telephone lines for allocation of the telephone lines by the virtual private network to the remote users.

Abstract: An electrostatic discharge (ESD) protection circuit comprises a P-channel field effect transistor (PFET), a buffer and a damping network to provide improved protection for an integrated circuit against high-voltage ESD pulses. The ESD protection circuit is capable of being fabricated with a reduced surface area layout to be fully synthesisable with the integrated circuit which it is designed to protect.

Abstract: An apparatus and method of calibrating a signal sourcing device having a plurality of signal sources to reduce errors between signals generated by the signal sources by categorizing the signal sources into groups based on the amount of error in the signal generated by the signal sources and selecting the signal sources from the groups in a manner which reduces the overall error in selecting signals. For example, the signal sourcing device may be a digital to analog converter having a plurality of current sources that output currents which may have an error. Such an improved digital to analog converter would categorize the current sources into groups based on the amount of error in the current generated by the current sources and selecting the current sources from the groups in a manner which reduces the overall error in selecting signals for the conversion process. The groups may include a center group that straddles the median current generated by the current sources.

Abstract: A method for detecting dropouts in digital data transferred over a bus from a digital data source to a computer system. Each address in the computer system buffer memory is initialized to a selected code value known not to exist in the data to be transferred. After sequential transfer of data to the buffer memory, the presence of the selected code value in the buffer memory indicates that a dropout occured.

Abstract: A high-isolation, low-power high-speed multiplexer circuit suitably includes a buffer stage and a current steering tree stage. By employing common select lines for both stages of the circuit, both the input buffer and the deselected channel provide cumulative isolation for the deselected channels.

Abstract: Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems.

Abstract: Modern portable communications units, and in particular cellular telephones, can contain several frequency bands for receiving and several frequency bands for transmitting signals. Typically these units contain a baseband unit and a frequency synthesizer unit, which may be embodied as VLSI integrated circuits. The baseband unit commonly contains the user interfaces and control signals for controlling other portions of the circuitry. The second unit is sometimes called a frequency synthesizer unit. The second unit is dedicated to producing frequencies that are used by the communications system to create RF signals for broadcast and also to take RF signals and extract the modulated signal from them for decoding. As personal communications units have begun using an increasing number of bands it is often necessary to configure different filters to receive or broadcast the different bands. Typically, the baseband Integrated Circuit or separate circuitry does this filter configuration management.

Abstract: Phase-locked-loop based data and clock extraction comprising a phase detector that generates up and down pulses. Down pulses are maintained in width approximately equal to 1.5 unit intervals of a local sampling clock. Up pulses are allowed to vary with the phase relationship between the local sampling clock and an incoming encoded bit stream. The up pulses are allowed to vary between 1 and 2 unit intervals of the local sampling clock. The up and down pulses drive a charge pump D/A converter that generates a control voltage. The control voltage sets the frequency of the local sampling clock generated by a voltage controlled oscillator. Shift register controlled by a state machine and clocked by the local clock allows reception of complex data packets arriving by the encoded bit stream.

Abstract: A communication device, such as a cable modem, having a programmable media access controller (MAC) supported by a programmable CRC engine. The CRC engine computes CRC values for data written to it by the programmable MAC or other software process, thereby relieving processing circuitry of these computationally burdensome functions. The programmable nature of the CRC engine permits compliance with a wide variety standards, including evolving standards such as DOCSIS, without requiring expensive hardware upgrades. In one embodiment of the invention, the CRC engine may be initialized by the programmable MAC with an initial vector prior to CRC computations. The programmable MAC or other software then locates the data bytes (e.g., data frame header data) for which a CRC is to be computed. This information is written to a data register of the CRC engine and a CRC operation is performed. Based on the results, the programmable MAC may determine whether the CRC operation indicates valid data.

Abstract: In a phase detection circuit, an incoming data signal is fed to one D flip-flop which is enabled off of a rising or positive edge of the clock which in turn feeds its output to a second D flip-flop enabled off of the same clock edge. The same incoming data is also fed to a third D flip-flop which is enabled off of a falling or negative clock edge of the same clock signal. The output of which is in turn fed into a fourth D flip-flop which is enabled off of the same negative edge. The incoming data is also fed to a first XOR gate, along with the output of the first D flip-flop to generate the error phase detection signal. The outputs of the second and fourth D flip-flops are fed into a second XOR gate to generate the reference phase detection signal.

Abstract: A switch suitable for use in high-bandwidth environments is disclosed. The switch eliminates the need for inter-stage jitter compensation by determining the timing signals associated with each data input and then re-timing the data based upon the timing signals at the switch output. Bandwidth is conserved by routing timing signals through a multiplexer that preferably determines the difference between the timing signal and a reference signal, combines the difference signal with other difference signals calculated for other data inputs, and then transmits the multiplexed difference signals to a demultiplexer. Suitable multiplexing schemes include time division multiplexing, wavelength division multiplexing, code division multiple access (CDMA) multiplexing, as well as various combinations of suitable multiplexing methods.

Abstract: A technique for identifying the encoding law utilized by a central office codec may be implemented in a receive modem. The encoding law, which is typically dictated by the country in which the central office is located, is employed to generate a plurality of transmission levels during an initialization period associated with the modem system. The receive modem analyzes a number of these transmission levels to determine whether the levels have certain characteristics associated with the particular encoding law followed by the central office codec. When the receive modem detects the codec type, it may transmit a suitable identifier back to the transmit modem.

Abstract: A communication system for communication of data packets associated with a packet switched network is disclosed herein. The system includes a port processor, a segmentation and reassembly device, and a host processor. The port processor communicates data packets to and from at least one communication device and at least one destination. The segmentation and reassembly device routes data packets to and from the port processor and the at least one destination. The host processor establishes a virtual circuit between the port processor and the segmentation and reassembly device. The host processor further directs the port processor to communicate data traffic to the segmentation and reassembly device via the virtual circuit, whereby the port processor and segmentation and reassembly device exchange data directly via the virtual circuit without per-packet handling by the host processor of all data traffic.

Abstract: A speech coding system that employs hybrid linear prediction coding during extraction of linear prediction coefficients within ITU-Recommendation speech coding standards. The present invention is operable within linear prediction speech coding systems including code-excited linear prediction speech coding systems, and it provides for a substantially improved perceptual quality of reproduced speech signals when compared to conventional speech coding methods that employ the commonly known auto-correlation method that is based on minimizing the linear prediction coding (LPC) prediction error energy. The invention is operable to provide for high perceptual quality of reproduced speech signals having substantial differences of energy in various frequency bands.

Abstract: A decoder having a first decoder providing first decoded data. A deinterleaver is included for deinterleaving the first decoded data. A second decoder provides second decoded data based on the deinterleaved first decoded data. The second decoder provides at least one decode status signal indicative of second decoder operations. A pipeline decoder unit is included that is coupled to the second decoder. The pipeline decoder unit includes an encoder that receives the second decoded data and provides forced decision data, a multiplexer, and a third decoder that provides pipelined decoded data. The multiplexer is responsive to the at least one decode status signal to selectively constrain the pipelined decoded data to be at least partially dependent on the forced decision data.

Abstract: Circuitry and methodology for transferring a representation of a data signal between clock domains. In particular, the disclosure teaches a method for creating representations of signals input from a slow clock domain into a fast clock domain and vice versa. The methods and apparatus use a RAM-free architecture which may be easily incorporated into integrated circuits to enhance efficiency.

Abstract: A compression system and process employs a group of quantizers (or set of predefined quantized values) and involves the selection of the quantizers for each video frame or frame portion. For each frame portion, a selection of the most appropriate quantizer is made. The selection of which quantizer from the selection group is most appropriate for coding of a video frame or frame portion is based on a formula which takes account both the distortion (accuracy) and bit rate characteristics of each quantizer. The quantizer that exhibits the best combined distortion and bit rate characteristics is selected for coding the frame or frame portion. A similar formula, based on both distortion and bit rate characteristics, is used to select the particular quantization value within the quantizer set for each video signal value being coded.

Abstract: A speech compression system capable of encoding a speech signal into a bitstream for subsequent decoding to generate synthesized speech is disclosed. The speech compression system optimizes the bandwidth consumed by the bitstream by balancing the desired average bit rate with the perceptual quality of the reconstructed speech. The speech compression system comprises a full-rate codec, a half-rate codec, a quarter-rate codec and an eighth-rate codec. The codecs are selectively activated based on a rate selection. In addition, the full and half-rate codecs are selectively activated based on a type classification. Each codec is selectively activated to encode and decode the speech signals at different bit rates emphasizing different aspects of the speech signal to enhance overall quality of the synthesized speech.

Abstract: In one embodiment, a system includes but is not limited to a low-processor-load aggregation device interposed between a network and at least one network station, the low-processor-load aggregation device having: (a) at least one multi-channel device, the multi-channel device having at least one internal network tag associated with the at least one network station, and (b) a host-processor-controlled routing device operably coupled with the network, the host-processor-controlled routing device configured to coordinate at least one network address with the at least one internal network tag associated with the at least one network station. In another embodiment, a method includes but is not limited to coordinating an external network-station packet with an internal private-network address of a low-processor-load aggregation device.

Abstract: In one embodiment, a system includes but is not limited to a host processor operably coupled with a broadcast-capable switch; a first broadcast-packet-processing device operably coupled with the broadcast-capable switch; a second broadcast-packet-processing device operably coupled with the broadcast-capable switch; and at least one of the first broadcast-packet-processing device and the second broadcast-packet-processing device operably coupled with the host processor.