Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data.

Abstract: A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.

Abstract: A computer system couples multiple function units using channels having full-duplex, low power, point-to-point interconnect. Each function unit couples to the channel via a Channel Interface Block (CIB). The CIB includes a transmitter and a receiver. The receiver includes an integrating sampling capacitor, pass-gates having particular resistive characteristics, an auto-zero inverter, and a set of inverter stages for squaring the output of the inverter. These components are used to implement sampled-data methods and structures that perform received data extraction from the full-duplex channel signal.

Abstract: A zero delay continuous long term (LT) pre-processing method operable in a speech codec that introduces no delay. The present invention provides an elegant solution to perform long term (LT) pre-processing of the pitch lag of a speech signal to save a large number of bits required in various speech coding methods, including the code-excited linear prediction method. The present invention is ideal for speech coding standards and methods that any undesirable delay at the end of a speech frame of the speech signal. The present invention overcomes a significant limitation in the art of speech coding, in that, a speech coding system that performs the invention is operable while providing real time operation and introducing no delay whatsoever.

Abstract: An efficient method and circuitry for transferring various levels of power across a high voltage isolation barrier. In one embodiment of the invention, a data access arrangement (DAA) is provided with system side circuitry that provides power to line side circuitry via the high voltage isolation barrier. The line side circuitry includes voltage measurement circuitry, such as an analog-to-digital converter, that periodically measures the line side supply voltage. The resultant information is transmitted across the high voltage isolation barrier to the system side circuitry, where control circuitry or a software process compares the digital representation of the measured voltage level to a predetermined value. Based on the results of this comparison, the control circuitry may alter the amount of power transferred across the high voltage isolation barrier to the line side circuitry in order to optimize power transfer efficiency.

Abstract: A diode for improved electrostatic discharge (ESD) protection against current failure includes a plurality of elongate anode and cathode conductor stripes each having first and second end portions of different widths to reduce current densities at feeder bus tie points, thereby reducing the possibility of current failure.

Abstract: An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate electrode and a gate oxide layer wherein nitrogen is selectively implanted into the gate oxide/device substrate interface prior to oxidation of the gate oxide layer. The nitrogen is selectively implanted so that the nitrogen is implanted into thin gate oxide regions and masked from thick gate oxide regions so that the benefits of controlling the boron penetration are realized while the 1/f noise is reduced due to the selective implantation of the nitrogen.

Abstract: PLL frequency synthesizers and their calibration techniques are described. The PLL frequency synthesizers are used to generate digital modulation of a carrier signal. A digital frequency divider in the feedback path of the loop has its division ratio controlled by a digital &Dgr;-&Sgr; modulator. The modulation of the carrier is achieved by applying a modulation signal to the input of the &Dgr;-&Sgr; modulator and to the input of the voltage-controlled oscillator of the PLL. The high frequency path and low frequency path of the modulation signal must be adjusted with respect to one another in order to obtain a good modulation. As the low frequency path can be accurately set, the calibration is performed only on the high frequency path. Digital calibration techniques for the high frequency path are described.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.

Abstract: An intermediate frequency amplifier for wireless communication applications has the same receive path and transmit path through an off-chip filter. The intermediate frequency amplifier circuit includes a first amplifier and a second amplifier. The second amplifier includes a gain control circuitry. The second amplifier provides gain control for both the receive mode and for the transmit mode of operation. The IF amplifier can be used in a variety of communication applications, including cordless telephones, cellular phones, PHS phones, wireless modems, radios, and other devices.

Abstract: A dual mode phone system utilizes a single transmit-receive (TR) switch. The dual mode system operates in GSM and DCS communication bands. The use of the single switch reduces the circuit board space required for the telephone hand set. Additionally, the architecture for the telephone reduces receiver losses associated with a diplexer in the receive path.

Abstract: A fully backward compatible intelligent discontinued transmission (DTX) and comfort noise generation (CNG) scheme that is operable in pulse code modulation (PCM) speech coding systems. The scheme, for example, provides a speech encoder comprising a speech signal analysis circuitry configured to calculates a predetermined plurality of parameters from the speech signal, a voice activity detector configured to determine voice activity in the speech signal, where the speech encoder enters a discontinued transmission mode of the voice activity detector does not detect voice activity, and a transmitter configured to transmit one or more speech samples of the speech signal after the speech encoder enters the discontinued transmission mode, where the one or more speech samples are capable of use by a remote speech decoder to extract a parameter from the one or more speech samples in order generate a background noise base on the parameter.

Abstract: A multi-rate speech codec supports a plurality of encoding bit rate modes by adaptively selecting encoding bit rate modes to match communication channel restrictions. In higher bit rate encoding modes, an accurate representation of speech through CELP (code excited linear prediction) and other associated modeling parameters are generated for higher quality decoding and reproduction. To achieve high quality in lower bit rate encoding modes, the speech encoder departs from the strict waveform matching criteria of regular CELP coders and strives to identify significant perceptual features of the input signal. To support lower bit rate encoding modes, a variety of techniques are applied many of which involve the classification of the input signal. For each bit rate mode selected, pluralities of fixed or innovation subcodebooks are selected for use in generating innovation vectors.

Abstract: A modem system includes a programmable synchronization signal format that can be configured at a first modem in response to a request received from a second modem. The synchronization signal format may define a number of parameters of the synchronization signal, such as the sign pattern for symbols transmitted by the first modem during a training sequence. The specific parameters of the synchronization signal format may be associated with the design and operation of the second modem. For example, the particular timing recovery and automatic gain control schemes used by the receiver portion of the second modem may be optimally initialized with a synchronization signal having a specific length, amplitude, or spectrum. In one embodiment, a synchronization signal is configured to convey a single frequency tone for use during a synchronization routine. The modem system may also employ similar techniques to generate, transmit, and analyze a programmable line impairment learning signal.

Abstract: A speech-coding device includes a fixed codebook, an adaptive codebook, a short-term enhancement circuit, and a summing circuit. The short-term enhancement circuit connects an output of the fixed codebook to a summing circuit. The summing circuit adds an adaptive codebook contribution to a fixed codebook contribution. The short-term enhancement circuit can also be connected to a synthesis filter to emphasize the spectral formants in an encoder and a decoder.

Abstract: A phase detection circuit for a phase-locked loop clock recovery system is described which detects the phase difference between an incoming data signal and a clock. The phase detection circuit is configured to generate two phase detection signals, the difference of which is indicative of the phase error between the incoming data and the clock. The phase detection circuit provides improved performance at high frequencies as well as increased flexibility in design and fabrication. The phase detection circuit in one embodiment comprises four type-D flip-flops and two exclusive-OR (XOR) gates. An incoming data signal is fed to one D flip-flop which is enabled off of a rising or positive edge of the clock which in turn feeds its output to a second D flip-flop enabled off of the same clock edge. The same incoming data is also fed to a third D flip-flop which is enabled off of a falling or negative clock edge of the same clock signal.

Abstract: A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. A smoothing element is coupled to the input elements to receive the gapped clock signal and the reference clock signal. In one embodiment, the smoothing element generates a smoothed clock signal having one pulse for each of the pulses in the gapped clock signal and having a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.

Abstract: According to a disclosed embodiment, a base region is grown on a transistor region. A dielectric layer is next deposited over the base region. The dielectric layer can comprise, for example, silicon dioxide, silicon nitride, or a suitable low-k dielectric. Subsequently, an opening is fabricated in the dielectric layer, and an emitter layer is formed on top of the dielectric layer and in the opening. Thereafter, an anisotropic polymerizing etch chemistry is utilized to etch the emitter layer down to a first depth, forming an emitter region in the opening. Next, a non-polymerizing etch chemistry having isotropic components is used to create a notch in the dielectric layer below the emitter region. The formation of the notch reduces the overlap area of a capacitor that forms between the emitter region and the base region, which translates to a lower level of emitter to base capacitance.

Abstract: Double balanced mixers having transistor pairs are affected by area mismatches between the transistors. The area mismatches can be represented as a ratio between the mixer core transistors that is directly related to voltage. Thus, an input voltage into one of the mixer core transistors in a transistor pair can compensate for the area mismatch. The compensation is achieved by a voltage track and hold feedback loop to one of the mixer core transistors.