Abstract: A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate.

Abstract: A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: Method and apparatus of parallel processing of multiple inference rules organized in fuzzy sets or logical functions of multiple fuzzy sets including membership functions defined in a so-called universe of discourse. The inference rules are configured essentially as IF-THEN rules with at least one antecedent preposition and at least one consequent implication. The prepositions have at least one term of comparison between membership functions and a plurality of input data and each term is separated by logical operators. The method associates with the logical operators maximum and minimum operations among two or more elements and calculates exhaustively the overall degree of truth (&OHgr;) of a rule with a maximum or minimum of N partial truth levels. The method is accomplished by a plurality of identical, parallel inferential processors. Each inferential processor determines a preposition or a partial truth level of a preposition.

Abstract: A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first conductivity type contained in the lightly doped semiconductor regions and defining channel regions. The lightly doped semiconductor regions are contained in respective enhancement regions of the lightly doped semiconductor layer of the same conductivity type as, but with a lower resistivity than, the lightly doped semiconductor layer.

Abstract: An apparatus over or under approximates the result of dividing a binary number representing an integer 2n. The division by 2n is performed by truncating the n least significant bits of the integer. In order to over or under approximate the result, the nth truncated bit, i.e., the most significant bit of the n-truncated less significant bits, is added to the integer represented by the remaining non-truncated bits.

Abstract: In a method, according to the invention, of storing one or more natural membership functions of respectively one or more natural variables being each defined within a natural universe of discourse having a lowest natural value and a highest natural value, the natural membership functions are normalized through respective normalization coefficients so that they are defined within the same predetermined absolute universe of discourse having a lowest absolute value and a highest absolute value, thereby obtaining one or more absolute membership functions, respectively, and said absolute membership functions and said normalization coefficients are stored, taking account that identical absolute membership functions are stored only once.

Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.

Abstract: A zero thermal budget manufacturing process for a MOS-technology power device.

Abstract: A high-speed bipolar-to-CMOS logic converter circuit, including an input stage, including a differential amplifier meant to be connected to a bipolar-logic circuit portion and to be supplied by the supply voltage of the bipolar-logic portion, and an output stage, which is supplied by the voltage of a CMOS-logic circuit portion, a dynamic level shifting circuit interposed between the input stage and the output stage, the output stage being connected to the CMOS-logic circuit portion.

Abstract: A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: An integrated semiconductor structure comprises two homologous P-type regions formed within an N-type epitaxial layer. A P-type region formed in the portion of the epitaxial layer disposed between the two P-type regions includes within it an N-type region. This N region is electrically connected to the P region by means of a surface metal contact. The structure reduces the injection of current between the first and second P regions, at the same time preventing any vertical parasitic transistors from being switched on.

Abstract: The invention relates to a modular architecture of a cellular network for improved large-scale integration, of the type which comprises a plurality of fuzzy cellular elements (C.sub.m,n) interconnected to form a matrix of elements having at least m rows and n columns, the row and column numbers describing the location of each element. Each fuzzy processor is adapted for connection to other processors of the same type such that a parallel architecture of the modular type can be implemented. The management of the architecture is facilitated by each submatrix being controlled by an individually dedicated fuzzy processor device.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A monolithically integrated power device for driving electrical loads includes a power stage having a high-voltage bipolar transistor and a low-voltage auxiliary transistor cascade-connected and inserted between a first power supply terminal and a second power supply terminal of the device. The power device also includes a driver circuit for the power stage having an input connected to an input terminal of the device. In accordance with the present invention the device includes a circuit for protection thereof against an excessive temperature rise and controlling power down of the power stage.

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of body stripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion.

Abstract: A neural cellular network for implementing a so-called Chua's circuit, and comprising at least first, second and third cells having respective first and second input terminals and respective state terminals, the first and second input terminals being to receive a first and a second reference signal, respectively, and the first cell, and the second and third cells being of mutually different types.

Abstract: The invention relates to a control circuit for semiconductor devices which is formed on a substrate (1) doped by a first dopant type, the integrated circuit comprising a first epitaxial layer (2) grown on the substrate (1) and doped by the first dopant type, and an isolation well (3) doped by a second dopant type, the control circuit comprising at least a first control transistor (M1) formed in a first well (8) doped by the second dopant type and formed in the insulation well (3). Thus, the control circuit comprises at least one N-channel MOS transistor accommodated within a well in direct contact with the isolation well to eliminate a buried layer that, in prior art arrangements, involved the presence of an undesired parasitic component.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window.

Abstract: A method of fabricating a junction-isolated semiconductor device is provided which includes the following steps. Within a first P-type buried region second N-type buried regions are formed. Over the first and second buried regions, an N-type epitaxial layer defining a surface of the device is grown. In the epitaxial layer, P-type isolation regions extending from the surface down to and in electric continuity with the first buried region and defining, with the first buried region, N-type wells incorporating the second buried regions is formed. And, P-type annular border regions in the epitaxial layer and to the side of the isolation regions are formed. The steps of forming isolation regions and annular border regions semiconducting regions being performed in a single step of selectively introducing doping ions.