Abstract: A metallization and bonding process for manufacturing a power semiconductor device includes a step of depositing a first metal layer over the entire surface of a chip; a step of selectively etching of the first metal layer to form desired patterns of metal interconnection lines between components previously defined; a step of depositing a layer of passivating material over the entire surface of the chip; a step of selectively etching of the layer of passivating material down to the first metal layer to define bonding areas represented by uncovered portions of the first metal layer; a step of depositing of a thick second metal layer over the entire surface of the chip; a step of selectively etching of the second metal layer down to the layer of passivating material to remove the second metal layer outside the bonding areas; and a step of connecting bonding wires to the surface of the second metal layer in correspondence of said bonding areas.

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor.

Abstract: Semiconductor device chips having a first layer of semiconductor material, a second layer of a semiconductor material and an insulating layer disposed therebetween. The first layer of semiconductor material has doped semiconductor regions disposed therein, and the second layer of semiconductor material has a power device disposed therein. The power device is disposed beneath the doped semiconductor region of the first layer. Trenches may be located within the first layer of semiconductor material to electrically isolate different areas having doped semiconductor regions. The insulating layer is typically formed from an oxide.

Abstract: A particle-detector is formed on a die of semiconductor material (20) comprising: first and second layers (22, 23) with a first type of conductivity (N), a third layer (21) with a second type of conductivity (P), interposed between the first and second layers (22, 23), first and second means (25, 31; 26, 32) for electrical connection with the first and second layers (22, 23), respectively, disposed on the opposite surfaces thereof to those of the junctions with the third layer (21) and third means (27, 24) for electrical connection with the third layer (21).To permit large-scale industrial manufacture, the third means (27, 24) for electrical connection with the third layer (21) comprise a region (24) with the second type of conductivity (P) which extends from the front face of the die as far as the third layer (21) and means (27) for surface electrical contact with this region.

Abstract: A three-state CMOS output buffer circuit includes a final amplifier stage having a pull-up transistor and a pull-down transistor connected between a voltage supply and ground and having a common output node, and a control circuitry for driving the final amplifier stage including a first logic gate supplied with an input data signal and an enable/disable signal for activating a three-state mode in which the pull-up transistor and the pull-down transistor are both deactivated, the first logic gate driving the pull-up transistor, a second logic gate supplied with said input data signal and enable/disable signal, the second logic gate driving the pull-down transistor. The pull-up transistor has a bulk electrode connected to a switchable bulk line; an auxiliary circuit is provided which as long as a voltage of the output node is not higher than said supply voltage keeps said switchable bulk line connected to the voltage supply.

Abstract: A process for manufacturing a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional its is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates

Abstract: A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of bodystripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion.

Abstract: A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first conductivity type contained in the lightly doped semiconductor regions and defining channel regions. The lightly doped semiconductor regions are contained in respective enhancement regions of the lightly doped semiconductor layer of the same conductivity type as, but with a lower resistivity than, the lightly doped semiconductor layer.

Abstract: A driver circuit delays the turning on of a MOS transistor by utilizing the time-wise pattern of the circuit input signal rather than generating a delay within the circuit itself. A threshold type of circuit element is arranged so that no current flows toward or from, depending on the type of the MOS transistor, the control terminal before the voltage at the circuit input exceeds a predetermined value. This is achieved, for example, by coupling a Zener diode serially to the control terminal. Where the input signal is of a kind which increases with a degree of uniformity, the time required to exceed that threshold will correspond to the desired delay. Thus, the driver circuit can match the dynamic range of the input signal automatically.

Abstract: The system includes various circuit units each having a capacitor and a charging circuit for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop which uses one of the circuit units as an adjustable oscillator, and current transducer means which regulates the charging currents of the capacitors of the circuit units in dependence on the regulated charging current of the capacitor of the oscillator, or the error current of the PLL loop.

Abstract: A power MOS chip and package assembly is provided for packaging a power MOS chip that has high heat dissipation. The assembly maintains a low contact resistance to the chip using compression without damaging the chip. The package assembly includes a thermally conductive body, a chip, an electrically conductive contact washer and an external electrical terminal. The chip includes a semiconductor substrate layer, an insulating layer, a conductive material gate layer and a metal layer. The layers form a plurality of first regions that are functionally inactive and a plurality of second regions. The insulating layer is formed to be thicker in the first regions than in the second regions so that the metal layer is elevated with respect to the substrate layer by a greater amount in the first regions than in the second regions. The contact washer is placed in mechanical contact with the chip so that it exerts pressure against the metal layer in the first regions to create an electrical connection.

Abstract: A process forms a MOS-technology power device including a semiconductor material layer of a first conductivity type and a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type. The process includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. A dopant of the second conductivity type is implanted twice at different concentrations and energies into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer.

Abstract: This invention relates to a fuzzy processor having an input X for at least a plurality of input variables X-i and an output U for one or more output results U-k, and including a fuzzyfication unit FU having an input coupled to the input X, a fuzzy rule processing unit RU having an input coupled to the output of the fuzzyfication unit FU, and a defuzzyfication unit DU having an input coupled to the output of the processing unit CU and an output coupled to said output U, wherein the output of the defuzzyfication unit DU is coupled to the input of the fuzzyfication unit FU and/or to the input of the processing unit RU.

Abstract: A sense and protection circuit against short circuits for digital outputs, comprising a logic gating circuit of the exclusive OR type (EX1) which has a first input terminal connected to a signal input node (IN) and an output terminal which is connected to an input terminal of a signal level shifter output stage (B). A second logic gating circuit of the exclusive OR type (EX2) has a first input terminal connected to the input node (IN) and a second input terminal connected, through an inverting circuit (IN1), to an output terminal (OUT) of the output stage (B). A second input terminal of the first logic gate circuit is coupled to an output terminal of the second logic gate circuit through a comparator circuit (SCH1) and a delay circuit means (C,R,D).

Abstract: A method and device for maintaining junction isolation between a second region that is normally clamped at a reference potential, contained within a first region of an opposite type of conductivity whose potential is subject to large inertial swings. The junction is ensured even when the potential of the first region moves toward and beyond the reference potential to which the second region is clamped, by connecting the second region to the reference potential by a switch, and causing the switch to open which places the second region in a floating state, leaving it free to track the potential excursion of the first region. The switch is closed after the potential of the first region has returned to a normal value. A comparator senses a shift of the potential of the second region from the reference potential to which it is clamped. The shift is dynamically induced by the capacitive coupling of the two regions, and triggers off the clamping switch.

Abstract: Analog processor of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators of membership function each having an output supplying a value corresponding to a degree of truth complemented to one (.alpha.') of logical assignments of the type (A is A') with the outputs being connected together to form a common circuit node and also connected to a current generator and the processor comprising also a voltage control device inserted between a supply voltage pole and a ground voltage reference and a one-way element connected to the common circuit node and the one-way element having an output producing an overall degree of truth for the antecedent part of the fuzzy rule to be processed.

Abstract: A phase-lock loop circuit with fuzzy control, includes a phase comparator whose output is connected to a low-pass filter that drives a voltage-controlled oscillator. The phase comparator generates a signal that represents the phase difference between an input signal and a signal generated by the oscillator. The oscillator of the present invention is furthermore driven by a control signal generated by fuzzy control. The input of the fuzzy control is the signal that represents the phase difference.

Abstract: A power MOS chip and package assembly is provided for packaging a power MOS chip that has high heat dissipation. The assembly maintains a low contact resistance to the chip using compression without damaging the chip. The package assembly includes a thermally conductive body, a chip, an electrically conductive contact washer and an external electrical terminal. The chip includes a semiconductor substrate layer, an insulating layer, a conductive material gate layer and a metal layer. The layers form a plurality of first regions that are functionally inactive and a plurality of second regions. The insulating layer is formed to be thicker in the first regions than in the second regions so that the metal layer is elevated with respect to the substrate layer by a greater amount in the first regions than in the second regions. The contact washer is placed in mechanical contact with the chip so that it exerts pressure against the metal layer in the first regions to create an electrical connection.

Abstract: A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.

Abstract: A circuit for biasing epitaxial wells of a semiconductor integrated circuit includes a first transistor and a second transistor driven in phase opposition to the first; when the supply voltage is positive, the first transistor, being connected between the power supply and the epitaxial well, is conducting whereas the second transistor is cut off. When, on the contrary, the supply voltage is negative, the second transistor, being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.