Abstract: A process for manufacturing integrated circuits includes the following steps. First, an oxide layer is formed on at least one surface of two respective semiconductor material wafers. Next, a single semiconductor material wafer is obtained with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from said two semiconductor material wafers by direct bonding of the oxide layers previously grown. The single wafer is submitted to a controlled reduction of the thickness of the first layer of semiconductor material and the top surface of the first layer of semiconductor material is lapped. Dopant impurities are selectively introduced into selected regions of the first layer of semiconductor material to form the desired integrated components.

Abstract: A diagnostic signal, indicative of the reaching of a predefined level, lower than a fixed maximum limit value, by the current flowing through a power transistor, is generated while employing a single comparator of a reference voltage with the voltage present across a sensing resistance, thus preventing problems arising from different offset characteristics of distinct comparators. By the use of current mirrors, the generation of a diagnostic signal when the current reaches a level that can be fixed very close to the maximum limit value, may be reliably triggered, irrespectively of the offset characteristic of the single comparator employed.

Abstract: Circuit for calculation of values of membership functions in a controller operating with fuzzy logic procedures. The membership functions are of triangular or trapezoidal form and are defined in a so-called discourse universe discretized in a finite number of points. The controller includes a central control unit equipped with a memory section for storage of said membership functions, a microprocessor, and an interface. The membership functions are stored by means of a codification of the coordinate of the vertex and the slopes at the sides of the vertex. The circuit includes a calculator connected to the memory section, the microprocessor, and the interface, to determine the value of each membership functions at each point of the discourse universe using the stored vertex and slopes.

Abstract: A PIC structure comprises a lightly doped semiconductor layer of a first conductivity type, superimposed over a heavily doped semiconductor substrate of the first conductivity type, wherein a power stage and a driving and control circuitry including first conductivity type-channel MOSFETs and second conductivity type-channel MOSFETs are integrated; the first conductivity type-channel and the second conductivity type-channel MOSFETs are provided inside second conductivity type and first conductivity type well regions, respectively, which are included in at least one isolated lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolation region of a second conductivity type.

Abstract: The base region of the power stage and the horizontal isolation region of the integrated control circuit or collector region of a transistor of an integrated circuit consist of portions of an epitaxial layer with a first conductivity type grown in sequence on an underlying epitaxial layer with a second conductivity type opposite the first.

Abstract: An integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.

Abstract: A filter architecture particularly for video applications, includes a filter section for separating high pass and low pass components from a video input signal conveying a video image, a brilliance estimating section for determining a mean brilliance value for each of a plurality of sections into which the video image is divided, first and second image characteristic adjusting sections for modifying the high pass and low pass components in response to the mean brilliance values, and a summing section for combining the modified high pass and low pass components to generate a filtered video signal. The first and second image characteristic adjusting sections operate using Fuzzy Logic which enables the filter architecture to effectively adjust contrast and brightness in the video image over a wide range of image brightness values.

Abstract: An electro-luminescent material and solid state electro-luminescent device comprising a mixed material layer formed of a mixture of silicon and silicon oxide doped with rare earth ions so as to show intense room-temperature photo- and electro-luminescence is described. The luminescence is due to internal transitions of the rare earth ions. The mixed material layer has an oxygen content ranging from 1 to 65 atomic % and is produced by vapor deposition and rare earth ions implant. A separated implant with elements of the V or III column of the periodic table of elements gives rise to a PN junction. The so obtained structure is then subjected to thermal treatment in the range 400.degree.-1100.degree. C.

Abstract: There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.

Abstract: An integrated circuit containing both power and small-signal NPN bipolar devices. The small-signal devices use lateral current flow, and are completely surrounded (laterally and vertically) by an N-type well region. The N-type well region itself is completely surrounded (laterally and vertically) by a P-type isolation region. This double isolation provides improved protection against turn-on of parasitic devices, which can cause leakage problems in the conventional device structures. Optionally a self-aligned process step is used to provide a graded base doping profile in the small-signal devices.

Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.

Abstract: The turn-off delay time of a low-side driver (output power transistor), may be independently reduced and eventually made identical to the turn-on delay time by employing an auxiliary current generator that may be controlled by the same switching signal that controls a current generator employed for discharging the control node of the low-side driver, in order to provide an augmented discharging current during a first phase (only) of a turn-off process. The contribution to the capacitance discharge current provided by said third current generator is automatically interrupted by means responsive to the voltage present on the driving node of the low-side driver, when it approaches saturation.

Abstract: An integrated structure active clamp for the protection of a semiconductor power device against overvoltages includes at least one first diode and at least one second diode defined in a lightly doped layer of a first conductivity type in which the power device is also disposed. The first diode has a first electrode connected to a control electrode of the power device and a second electrode connected to a second electrode of the second diode. The second diode has a first electrode connected to a load driving electrode of the power device. The second electrode of the second diode is represented by a first buried region of a second conductivity type, which is buried in the lightly doped layer, and the first electrode of the second diode is represented by a first doped region of the first conductivity type which extends from a semiconductor top surface into the lightly doped layer to partially overlap the first buried region.

Abstract: An integrated structure is described, that comprises a vertical bipolar transistor and a vertical MOSFET transistor, where, in order to reduce the series resistance of the MOSFET transistor, the collector region of the bipolar transistor and the drain region of the MOSFET transistor are both parts of a common zone and are contiguous each other, so that the high charge injection in the collector region when the bipolar transistor is in conduction state, causes a simultaneous increase in the conductivity of the drain region of the MOSFET transistor.Both transistors are formed by cells each containing an elementary bipolar transistor and an elementary MOSFET transistor.

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter.

Abstract: A method for connecting a wire lead between a semiconductor circuit chip and a corresponding terminal connector of a semiconductor device includes providing a bonding tool having a working end formed with at least a pair of grooves of different length, holding one end of the wire lead to the pin of the semiconductor device in one of said grooves and bonding it, and holding the other end of said wire to the chip in the other of said grooves an bonding it. The grooves have different lengths to allow for different wire spans across the bonded connection areas, on the chip and the pins.

Abstract: A method for eliminating the bird's beak from selective oxidations of semiconductor electronic devices having a semiconductor substrate (1) which is covered by a pad oxide layer (2) covered, in turn, by a first layer (3) of nitride, and wherein at least one vertical-walled pit (11) is defined for growing an isolation region, comprises the sequential steps of: selectively etching the oxide layer (2) within the pit (11) to define peripheral recesses (6,8) between the substrate (1) and the nitride; filling the recesses (6,8) with nitride; and growing oxide in the pit (11) so as to form the isolation region contrasting the nitride portions (9,10) which occlude the recesses (6,8).

Abstract: The invention relates to a method and a generator for producing an aluminum ion flow, specifically for aluminum ion implantation in the microelectronics industry.

Abstract: In integrated structure sensing resistor for a power MOS device consists of a doped region extending from a deep body region of at least one cell of a first plurality of cells, constituting a main power device, to a deep body region of a corresponding cell of a second smaller plurality of cells constituting a current sensing device.

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.