Abstract: A large-scale integrated circuit (LSI) chip has an individual voltage level sensing circuit connected with each input and output connecting pin so that isolation between the pins is maintained and so that the individual level sensor output can provide an indication of an abnormal voltage on the input/output pin. The outputs of all level sensors for all input and output pins is connected in common to the input of a comparator circuit. The comparator circuit has a fault detection threshold voltage input and provides a fault indication output signal whenever the voltage input from the level sensor circuits is outside of the detection threshold voltage range. A number of logic chips will have particular input/output pins connected together in a circuit in conventional applications. An open circuit anywhere in the interconnected network will cause some number of input/output pins dependent on the fault location to be pulled out of the detection threshold voltage range.

Abstract: A multi-channel EBAL apparatus and method of operation employing a plurality of parallel operated electron beam channels with each electron beam channel being of the fly's eye array optics type having an electron gun for producing an electron beam, an array lenslet assembly and an associated fine deflector assembly together with a coarse deflector for selectively directing the electron beam to a desired array lenslet within the array lenslet assembly. The associated fine deflector element thereafter directs the electron beam to a desired point on a target surface such as a target semiconductor wafer being processed by electron beam lithography. A common movable stage is provided for supporting the target wafer surfaces below the plurality of parallel operated electron beam channels and for moving the target surfaces in common relative to the array optics axes of all of the electron beam channels.

Abstract: A method is presented for demultiplexing two or more streams of data multiplexed in a phase shifted arrangement. Demultiplexing is accomplished by multiplying the composite signal by an individual correlator signal for each data stream, each correlator signal being mutually orthogonal with the other correlator signals.

Abstract: The microinstructions controlling a pipeline processor are held in a control store that is partitioned into two microcode memory banks. The invention can support three modes of sequencing; single microinstruction, sequential multiple microinstructions, and multiple microinstructions with conditional branching. When a conditional branch is performed, the branch not taken path is assumed and if true, the microinstruction following the branch is executed with no delay. If the branch is taken, the guess is purged and following a one clock delay, the branched to microinstruction is executed. The invention supports these sequencing modes at the maximum pipeline rate, since the only logic between registers is the memory chips.

Abstract: Electron-beam stage X-Y positioning instrumentation is provided. The electron-beam stage has a number of metal blocks affixed to its bottom. Fixed orthogonal noncontact gage heads are used to sense the distance of the heads from the parallel faces of a proximate metal block. The position of the metal block vis-a-vis the position of the fixed referenced gage heads yields the X-Y coordinates of the stage. The stage is first coarsely positioned adjacent a preselected block.Thereafter the exact position of the stage is computed from the distances sensed by the gage heads. The electron beam electronics are automatically adjusted to the actual position of the stage thereby eliminating the relatively slow, fine positioning of the stage.

Abstract: This invention is an electronically steerable radar antenna which is on a cylinder section which is on the order of one wave length in circumference and in which the shape of the antenna elements on the cylinder section take the form of "O", "I" and "C" slots occupying about one-third the section circumference. Radar beams are steered by changing the phase and amplitude of the drive to the different elements of the antenna. The slots are formed as interruptions in an otherwise continuous, conductive ground plane and may be filled with dielectric if desired so that there is no surface discontinuity.

Abstract: Apparatus is disclosed for processing sparse vectors in a tandem or parallel processing environment. Sparce vectors are those vectors stored in memory with their zero-valued operands deleted. They have a corresponding order vector of bits whose state indicates the order of zero and non zero operands in a corresponding expanded vector. The apparatus fetches the order vectors n bits at a time, n corresponding to the number of tandem processors, and counts the number of one bits. This number of operands is then fetched from memory. The apparatus aligns and orders the fetched sparse vector operands, inserts zero operands where appropriate, and forwards the resulting portion of the expanded vector to the tandem processors for processing.

Abstract: A cache memory organization is shown using a miss information collection and manipulation system to insure the transparency of cache misses. This system makes use of the fact that the cache memory has a faster rate of operation than the rate of operation of central memory. The cache memory consists of a set-associative cache section consisting of tag arrays and control with a cache buffer, a central memory interface block consisting of a memory requester and memory receiver together with miss information holding registers section consisting of a miss comparator and status collection device. The miss information holding register section allows for an almost continual stream of new requests for data to be supplied to the cache memory at the cache hit rate throughput.

Abstract: A system is provided for predicting in advance the result of a conditional branch instruction in a computer system. The system includes a hash mechanism, a random access memory, an address buffer, a branch outcome result receiving means and a counter buffer. The hash mechanism and memory use the input branch instruction address to produce a count which in effect is a way of weighting recent branch history to predict the branch decision. The counts are stored in the random access memory (RAM). The random access memory is addressed by the hashed branch instruction address to produce the system result.

Abstract: A demand driven access mechanism comprises logic apparatus at each station capable of seizing use of a shared communication channel for enabling access to a selected one station. The logic apparatus receives status signals from all stations so that if one station seeks access to the channel it will be enabled immediately upon an inactive status to the channel. If two or more stations simultaneously seek access to the channel, the logic apparatus establishes a priority order between them, thereby enabling access to only one station at a time. The priority ordering is based, in part, by the identity of the station last enabled, to thereby assure priority order allocation among the stations.

Abstract: A modified least recently used resolving network provides the capability of ignoring any one or more of the signals indicating use of the device in resolving the least recently used status of the devices.

Abstract: A test system performs dynamic testing of complex logic modules at full system clock rates and is resident on each LSI chip under test. The system logic is designed to be included on each LSI chip to reduce the time and computation required to detect and isolate faults in systems built from one or more chips. The on chip system includes switchable transmission gates to alter logic paths, a control shift register in the test function, an input shift register, an associated test generator and accumulator, an output shift register and an associated generator and accumulator. This logic provides test operands for the logic function under test and analyzes the resultant operands. Test operands are produced using a shift register connected to all inputs of the logic function under test. Checksum logic together with a shift register produce a running checksum of all output states of the module under test at the operative clock rate of the LSI.

Abstract: In this apparatus for dynamically translating virtual memory addresses to real memory addresses, a master system page table maintained in a memory associates real memory addresses with their corresponding system virtual memory addresses. This table is organized with each virtual memory address stored in it at an index location which is a smaller value formed as a predetermined function of the virtual memory address value. The translator forms the index from the virtual memory address according to the function, enters the table with it, and extracts the corresponding real memory address. In a preferred embodiment, every process (i.e., job) may reference any address in any segment of a process virtual address space, and a dedicated mechanism converts such a process virtual address reference to a system virtual memory address, which then is converted to the real memory address.

Abstract: An electron beam or other charged particle beam tube of the compound fly's eye type having a coarse deflection system is described. The beam tube comprises an evacuated housing together with an electron gun or other charged particle beam producing means disposed at one end of the evacuated housing for producing a beam of electrons or other charged particles. A coarse deflector, a compound micro lens assembly, and a fine deflector are disposed in the housing in the path of the electron or other charged particle beam for first selecting a lenslet and thereafter finely deflecting an electron or other charged particle beam to a desired spot on a target plane.

Abstract: A unipotential electrostatic lens and method of operation for charged particle beam tubes of the electron beam, compound fly's eye type having both coarse and fine deflection sections wherein the objective lens assembly may lack coaxial symmetry about the lens axis. The unipotential lens comprises an assembly of axially aligned electrostatic lens elements with each lens element having an array of micro lenslet apertures and with each set of axially aligned micro lenslet apertures forming a micro lenslet. Preferably, there are three such lens elements in the assembly with a high voltage excitation potential supplied to the center lens element. A dynamic focus correction potential derived from the deflection potentials applied to the tube is supplied to the entrance outer lens element closest to the electron gun of the beam tube. The remaining outer lens element is maintained at system ground reference potential.

Abstract: A delay lock loop has a fixed delay element, means for detecting the edge transitions of pulses, analog or digital feedback means related to the timing differences between the edge transitions of a pair of pulses and a variable delay means responsive to the feedback means for adjusting the timing differences between a pair of pulses in response to the feedback signals. In the analog embodiment, the feedback may be a voltage related feedback with a varying voltage controlling a voltage responsive variable delay means. In the digital embodiment, the feedback means may use a counter responsive to signals from an edge detecting flip-flop and the counter may control a programmable delay means.

Abstract: A time synchronization system involves a master station sending time information to a remote station and in which a portion of the time message is used as a trigger to start a counter or interval clock in the remote station. When the time message is concluded, the remote station adds the time in the interval clock or counter to the time from the message received to create an actual time which replaces the existing time information in the remote station clock. The time portion of the message sent represents the actual time at which the trigger in the time message was actuated and represents a later portion of the message as sent.

Abstract: In a microcode control memory for a computer central processing unit, a network is provided for generating a modified microcode address in a sequence of instructions where the modified address is determined by a function of the results of preselected events.

Abstract: A pilot cell driver for a capacitive memory plasma display device having three output states: high, low, and floating. The floating state of the pilot cell driver is used in combination with a feedback of the plasma display panel sustain voltage to create a third voltage level on the pilot cell drive line for use in rewriting the pilot cells. The pilot cell driver is comprised of a pull-up switch and pull-down switch. After the pull-up switch is activated for a short period of time, the output of the pilot cell driver relaxes to the floating state. The floating state voltage is achieved, for example, on a vertically oriented pilot cell drive line by coupling to a horizontal sustain drive voltage which switches from the pull-up voltage to the pull-down voltage during the relaxation time of the pilot cell driver. By capacitively coupling the horizontal sustain voltage to the vertical pilot cell drive electrode, the floating state voltage is achieved.

Abstract: A temperature compensated current source includes three successive source current paths to produce a controlled output current. Each current path has a different value of current flowing therein so that current fluctuations in one current path will tend to be isolated from the other current paths because of the difference in current flow. In the embodiment of the invention shown, a reference zener diode provides a reference voltage at the base of a first transistor to establish a first reference current as its emitter current. A second transistor uses the first current as the reference to establish a second current value which has a positive temperature coefficient. Third, fourth and fifth transistors use the second reference current to establish a third reference current value independent of the gain values of these transistors.