Abstract: A high-speed binary divider is provided which produces two quotient bits per processor cycle using two carry-save adders in a nonrestoring division mode with a delayed sign logic circuit selecting the adder having the required adder result for the current partial remainder.

Abstract: Apparatus is disclosed for removably mounting a printed circuit card to a chassis adapted to support an array of circuit cards. Two jackscrews are rotatably mounted to each circuit card by a bracket at each end of a row of electrical pin contacts. Mounted to the chassis at each end of a row of female electrical contacts is an anchor with a jackscrew-receiving opening. Insertion of the jackscrews into the anchors aligns the pin and the female contacts and turning of the jackscrews into the anchors then causes the pin and female contacts to electrically engage. Each jackscrew carries an internally threaded crown and a plurality of ramps between the crown and bracket. Each ramp is movable longitudinally of the jackscrew and also laterally by virtue of a bore therethrough larger in diameter than the jackscrew. The crown is movable toward and away from the bracket.

Abstract: A delay lock loop has a fixed delay element, means for detecting the edge transitions of pulses, analog or digital feedback means related to the timing differences between the edge transitions of a pair of pulses and a variable delay means responsive to the feedback means for adjusting the timing differences between a pair of pulses in response to the feedback signals. In the analog embodiment, the feedback may be a voltage related feedback with a varying voltage controlling a voltage responsive variable delay means. In the digital embodiment, the feedback means may use a counter responsive to signals from an edge detecting flip-flop and the counter may control a programmable delay means.

Abstract: A microcode addressing system is shown which has two modes of operation for different memory search functions. The first mode, the Slow mode in which the memory operates at a standard read rate, is the mode in which the computer central processing unit performs predetermined sequential tasks in a normal fashion. The second mode of operation is the Fast mode of operation in which the memory responds to unpredetermined, dynamically changing events in the computer system at a faster than standard cycle time in order to search for and identify a particular word in central memory.

Abstract: A monitor and control apparatus according to the present disclosure includes a configuration and environment monitor (CEM) connected to a plurality of remote station monitors of a computer system for executing commands at the remote stations and for monitoring abnormal conditions thereat. The remote monitors each include a Johnson counter responsive to clock signals from the CEM to sequentially step through its output positions. Address means is selectively connected to first output positions of the Johnson counter to provide a unique address for each remote monitor. Monitor means receives monitor condition signals and is arranged with a transmitter to transmit a signal to the CEM upon sensing a fault. The CEM then sequences the Johnson counters to cause the address and fault identification data in the operated monitor to be transmitted to the CEM.

Abstract: A register data transmission system has a plurality of register devices connected in series to form a data transmission link between a sending device and a receiving device. This register system can function between independent synchronous operating units of a computer such as a pair of data buffers. As data is transmitted, the individual register devices absorb the data as compactly as necessary within limits, to form the data path. Each register device has two data registers and two control flip-flops. The two data registers are the primary and secondary data rank registers. The secondary data rank register only receives data when the primary data rank register cannot receive data. The two control flip-flops are the primary and secondary full-bit flip-flops. Each register device has a clock control. In operation, data travels from the sending device through each register device to the receiving device while a control signal travels from the receiving device to the sending device.

Abstract: This disclosure is of a controlled environment agriculture facility in which a plurality of plant grow support racks are structured and arranged within a plant grow enclosure to define an air return passage from the enclosure with air ingress to such passage being distributed over surfaces of the racks. This provides good uniformity of air distribution within the enclosure and affords improved transportability and installation of the facility.

Abstract: This invention uses a plurality of bubble memory chips in a system for providing simultaneous input and output in a word or byte organized output. Each bubble memory chip has the same number of minor loops as is required for nominal memory size without the requirement for extra or redundant loops. Each bubble memory chip may have a number of faulty minor loops where the bit output is incorrect and cannot be used. However, a requirement for this system is that no two bubble memory chips may have a faulty bit or minor loop at the same major loop address location. An additional bubble memory chip is provided which will contain the correct data bits for locations corresponding to defective major loop addresses in the bubble memory chips making up the byte. A Programmable Read Only Memory (PROM) is provided and connected with a logic network to control the gating of the outputs of the bubble memory chips associated with the memory byte and the extra bubble memory chip to control the gating of the outputs.

Abstract: This is a system for connecting flexible electrical connectors having raised conductors above an insulating substrate to a plasma display panel having a glass substrate with the electrical conductors deposited in the bottom surface of conductor pathways etched in a glass substrate. The raised conductors on the connectors mate with the depressed conductors in the panel substrate. The spacing of the conductors in the connector may be varied to facilitate an exact mating with the conductors in the panel substrate. A clip device in combination with a flexible insulating force spreading member applies a uniform continuous pressure to the connector cable and glass substrate combination to maintain connection. This system may be used to facilitate the direct attachment of large scale integrated circuit chip carriers having conductor members on a surface thereof directly to conductors in a plasma display panel substrate.

Abstract: A bubble memory chip is manufactured using the following processing steps:a first dielectric insulation layer is deposited on the epitaxial garnet substrate, next,a comparatively thicker layer of a second dielectric insulator is deposited on the surface of the first layer of dielectric insulation, next,the reverse of the desired conductor image is printed on the surface of the second layer of dielectric insulator using a resist material such as a photoresist, next,a straight wall etching process is used to achieve a straight wall etching of the second layer of dielectric insulation but not affecting the first layer of dielectric insulation, next,the selected conductor material is deposited into the exposed groove from the previous etching process and over any remaining resist material such as a photoresist, next,a resist material is applied over the resulting conducting surface from the previous step, next,a course featured pattern is printed over the desired conductor regions leaving exposed the extensive su

Abstract: Apparatus for mounting a thin flexible grinding wheel to allow accurate cutting of kerfs therewith. A method of precision assembly of the apparatus is also disclosed.

Abstract: A method and apparatus for rotating priorities among stations on a communication channel, and particularly on a contention channel where a plurality of active stations are provided, each capable of seizing use of the channel. Counter means at each station contains an indication representative of the station having highest priority to the channel Each station establishes a priority rank for itself based upon the contents in the counter means. The indication is sequentially altered to provide priority to other stations. The priority indications in the counter means are synchronized each time a station seizes use of the channel, and may also be synchronized periodically if no station seizes use of the channel.

Abstract: An apparatus is disclosed for centering one or more magnetic discs on a rotatable spindle. The apparatus includes a disc-carrying hub having a circumferential collar, a central housing supporting a centering ball, and a diaphragm joining the collar and housing, stiff in the radial direction but allowing axial movement of the centering element with respect to the collar. The hub is attracted to a rotatable spindle by an annular permanent magnet mounted on the spindle opposite a similarly sized armature mounted on the hub. A cup formed in the spindle at its center receives the centering ball and guides it to the center of the spindle as the hub is attracted to the spindle. After the centering ball is seated in the center of the cup, the diaphragm flexes to allow continued axial movement of the collar to full engagement with the spindle.

Abstract: A polynomial generator for use in an error code correction system consists of an input data multiplexer for determining the mode of operation, a plurality of polynomial enable gates to allow insertion of a predetermined polynomial, a plurality of check character generating gates divided into a first group and a second group for forming an output polynomial from the input data and the predetermined polynomial, an output holding register and a pair of decode gates for constantly monitoring the contents of the holding register to provide an indication of either of two particular conditions.

Abstract: A multiplier for use with polynomials in an error correction system wherein the multiplier and multiplicand are first encoded from m bits to N bits, where N is greater than m, and wherein the multiplication is accomplished on a bit basis by arrays of AND gates and where the resultant product is decoded from R bits to S bits where S is less than R.

Abstract: A phase detector in a phase locked loop decoder includes a reactive circuit adapted to vary a clock frequency responsive to a signal representing the phase error between a clocking signal and an incoming data signal, to maintain synchronization of the clocking and data signals. A fast synchronization circuit of the phase detector is adapted to generate a clock-frequency-altering signal whenever selected inputs derived from the data and clocking signals occur simultaneously, thereby rapidly forcing the clocking signal toward synchronization with the data signal.

Abstract: A combined fine focusing micro lens array and micro deflector assembly for use in electron beam tubes of the fly's eye type is provided. The assembly comprises a fine focusing micro lens array sub-assembly formed from a plurality of spaced-apart stacked parallel thin planar apertured silicon semiconductor lens plates each having an array of micro lens aperture openings. The lens plates each have highly conductive surfaces and are secured to glass rods for holding the plates in stacked parallel spaced-apart relationship with the apertures axially aligned in parallel. A micro deflector assembly is adjacent to the micro lens array sub-assembly. A micro deflector element axially aligned with each respective fine focusing lens element serves for deflecting an electron beam passing through along orthogonal x-y directional axes of movement normal to the electron beam path.

Abstract: A method and apparatus is provided for eliminating conflicts on a communication channel, and particularly on a shared communication channel having a plurality of active stations, each capable of seizing use of the channel. A counter at each station contains a representation of the identity (address) of the station having the current opportunity to seize use of the channel. The representation is sequentially altered to provide the opportunity to each station to seize use of the channel, and each station not having such opportunity is inhibited from seizing the channel. The representations in the counters are synchronized each time a station seizes use of the channel, and may also be synchronized if no station seizes use of the channel.

Abstract: In a field access type bubble memory system using a major loop-minor loop organization, redundant loops are included in each memory chip so that defective minor loops may be disregarded and the memory retain its nominal capacity. Thus, the total number of loops is in excess of the nominal capacity. In one form of the invention the redundant loops are included with the minor loops. In another form of the invention, the redundant loops are independent of the minor loops. A stationary register or flaw chain having at least as many storage locations as the number of minor loops is located on the bubble memory chip with the major and minor loops. Each register location is assigned to contain information with respect to an assigned corresponding minor loop.

Abstract: A magnetic head is manufactured by depositing a layer of spacer material onto the facing surfaces of the magnetic cores; the thickness of each layer being approximately one-half the length of the intended gap and the thicknesses of both layers together being approximately equal to the thickness (length) of the gap. A layer of bonding glass is deposited onto the surfaces of the spacer layers and the cores are pressed together at an elevated temperature to fuse the glass layers and extrude most of the glass.