Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
Abstract: A wearable device has a core contraction sensor and a movement sensor which transmits signals to a processor which analyzes the signals. The core contraction signal may determine if the user's core is contracted or relaxed. A video camera on a smart device may be used with the wearable device to record video of a user while data from the sensors on the wearable device are also recorded. The core contraction and movement sensor data may be sent to and viewed on the smart device display together with video of the user performing a movement. The simultaneous viewing of the video and sensor data may provide immediate feedback to the user regarding the timing of core contractions with body movements in an athletic, training, or therapeutic movement to allow the user to modify and improve coordination of core contraction with body movements to improve movement performance and achieve better results.
Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
Type:
Application
Filed:
February 7, 2018
Publication date:
June 28, 2018
Applicant:
Hyperion Core, Inc.
Inventors:
Martin VORBACH, Frank MAY, Markus WEINHARDT
Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
Type:
Grant
Filed:
August 19, 2015
Date of Patent:
February 20, 2018
Assignee:
Hyperion Core, Inc.
Inventors:
Martin Vorbach, Frank May, Markus Weinhardt
Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
Abstract: Embodiments disclosed include a system and method for development of core muscles' support, comprising a means for identifying a user qualifying movement, a means for detecting a core muscle contraction in the identified qualifying movement, a means for discriminating between a core muscle contraction and no core muscle contraction in the identified qualifying movement; and a means to provide feedback to the user.
Type:
Grant
Filed:
December 19, 2013
Date of Patent:
October 24, 2017
Assignee:
Alert Core, Inc.
Inventors:
Gregory Takeo Uehara, Brian Taylor Brunn
Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
Abstract: A wearable device has user movement sensors and core contraction sensors. Signals from the sensors are transmitted to a processor which analyzes the movement signals and determines when a qualifying movement is performed which benefits from core contraction. Signals from the core contraction sensors are also transmitted to the processor and are used to determine if the core is contracted during the qualifying movement. If the core is contracted during the qualifying movement, the movement is a protected qualifying movement. However, if the core is not contracted during the qualifying movement the movement is an unprotected qualifying movement. The system can inform the user when unprotected qualifying movements are performed.
Abstract: The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
Abstract: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
Type:
Application
Filed:
August 19, 2015
Publication date:
February 18, 2016
Applicant:
HYPERION CORE, INC.
Inventors:
Martin VORBACH, Frank MAY, Markus WEINHARDT
Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
Abstract: Embodiments disclosed include a system and method for development of core muscles' support, comprising a means for identifying a user qualifying movement, a means for detecting a core muscle contraction in the identified qualifying movement, a means for discriminating between a core muscle contraction and no core muscle contraction in the identified qualifying movement; and a means to provide feedback to the user.
Type:
Grant
Filed:
December 18, 2013
Date of Patent:
January 5, 2016
Assignee:
Alert Core, Inc.
Inventors:
Gregory Takeo Uehara, Brian Taylor Brunn