Patents Assigned to Core Inc.
  • Patent number: 10331615
    Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 25, 2019
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Publication number: 20190171449
    Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
    Type: Application
    Filed: January 10, 2019
    Publication date: June 6, 2019
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Patent number: 10292647
    Abstract: A wearable device has a core contraction sensor and a movement sensor which transmits signals to a processor which analyzes the signals. The core contraction signal may determine if the user's core is contracted or relaxed. A video camera on a smart device may be used with the wearable device to record video of a user while data from the sensors on the wearable device are also recorded. The core contraction and movement sensor data may be sent to and viewed on the smart device display together with video of the user performing a movement. The simultaneous viewing of the video and sensor data may provide immediate feedback to the user regarding the timing of core contractions with body movements in an athletic, training, or therapeutic movement to allow the user to modify and improve coordination of core contraction with body movements to improve movement performance and achieve better results.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 21, 2019
    Assignee: Alert Core, Inc.
    Inventor: Gregory Takeo Uehara
  • Publication number: 20190079769
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 14, 2019
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Patent number: 10031888
    Abstract: The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: July 24, 2018
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Publication number: 20180181403
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 28, 2018
    Applicant: Hyperion Core, Inc.
    Inventors: Martin VORBACH, Frank MAY, Markus WEINHARDT
  • Patent number: 9898297
    Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 20, 2018
    Assignee: Hyperion Core, Inc.
    Inventors: Martin Vorbach, Frank May, Markus Weinhardt
  • Publication number: 20180039576
    Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
    Type: Application
    Filed: July 28, 2017
    Publication date: February 8, 2018
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Publication number: 20170364338
    Abstract: The present invention related to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
    Type: Application
    Filed: July 7, 2017
    Publication date: December 21, 2017
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Patent number: 9795337
    Abstract: Embodiments disclosed include a system and method for development of core muscles' support, comprising a means for identifying a user qualifying movement, a means for detecting a core muscle contraction in the identified qualifying movement, a means for discriminating between a core muscle contraction and no core muscle contraction in the identified qualifying movement; and a means to provide feedback to the user.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 24, 2017
    Assignee: Alert Core, Inc.
    Inventors: Gregory Takeo Uehara, Brian Taylor Brunn
  • Publication number: 20170262406
    Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Patent number: 9734064
    Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: August 15, 2017
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Patent number: 9706962
    Abstract: A wearable device has user movement sensors and core contraction sensors. Signals from the sensors are transmitted to a processor which analyzes the movement signals and determines when a qualifying movement is performed which benefits from core contraction. Signals from the core contraction sensors are also transmitted to the processor and are used to determine if the core is contracted during the qualifying movement. If the core is contracted during the qualifying movement, the movement is a protected qualifying movement. However, if the core is not contracted during the qualifying movement the movement is an unprotected qualifying movement. The system can inform the user when unprotected qualifying movements are performed.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: July 18, 2017
    Assignee: Alert Core, Inc.
    Inventor: Gregory Takeo Uehara
  • Patent number: 9703538
    Abstract: The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 11, 2017
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Patent number: 9672188
    Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: June 6, 2017
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Publication number: 20160306631
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyser unit located between the trace cache and the ALUs, wherein the analyser unit analyses the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 20, 2016
    Applicant: Hyperion Core, Inc.
    Inventor: Martin VORBACH
  • Patent number: 9348587
    Abstract: The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: May 24, 2016
    Assignee: Hyperion Core, Inc.
    Inventor: Martin Vorbach
  • Publication number: 20160048394
    Abstract: The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 18, 2016
    Applicant: HYPERION CORE, INC.
    Inventors: Martin VORBACH, Frank MAY, Markus WEINHARDT
  • Publication number: 20160004639
    Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said a least two cores, preferably at least four processor core, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at 1 a one node, preferably at least three nodes for a four processor. core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
    Type: Application
    Filed: July 3, 2015
    Publication date: January 7, 2016
    Applicant: HYPERION CORE INC.
    Inventor: Martin VORBACH
  • Patent number: 9226706
    Abstract: Embodiments disclosed include a system and method for development of core muscles' support, comprising a means for identifying a user qualifying movement, a means for detecting a core muscle contraction in the identified qualifying movement, a means for discriminating between a core muscle contraction and no core muscle contraction in the identified qualifying movement; and a means to provide feedback to the user.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: January 5, 2016
    Assignee: Alert Core, Inc.
    Inventors: Gregory Takeo Uehara, Brian Taylor Brunn