Abstract: A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1018 to 1×1020 atoms/cm3, a ratio of a screw dislocation density to the total dislocation density is from 0.15 to 0.3 in an interface region between the buffer layer and the active layer, and the total dislocation density in the interface region is 15×109 cm?2 or less.

Abstract: The present invention relates to a corrosion resistant member including: a substrate composed of a ceramic or a metal, and at least one layer of a corrosion resistant film formed on a surface of at least a region of the substrate to be exposed to plasma or a corrosive gas, in which the corrosion resistant film contains yttria as a main component and further also contains at least one of tantalum and niobium in an amount of 0.02 to 10 mol % in terms of pentoxide relative to the yttria, and a non-melted portion is not present in the corrosion resistant film.

Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.

Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.

Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.

Abstract: A nitride semiconductor substrate suitable for a normally-off type high breakdown-voltage device and a method of manufacturing the substrate are provided allowing both a higher threshold voltage and improvement in current collapse. In a nitride semiconductor substrate 10 having a substrate 1, a buffer layer 2 formed on one principal plane of the substrate 1, an intermediate layer 3 formed on the buffer layer 2, an electron transport layer 4 formed on the intermediate layer 3, and an electron supply layer 5 formed on the electron transport layer 4, the intermediate layer 3 has a thickness of 200 nm to 1500 nm and a carbon concentration of 5×1016 atoms/cm3 to 1×1018 atoms/cm3 and is of AlxGa1-xN (0.05?x?0.24), and the electron transport layer 4 has a thickness of 5 nm to 200 nm and is of AlyGa1-yN (0?y?0.04).

Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.

Abstract: A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm3, thereby forming a silicon oxide film on the surface of the silicon wafer, a second step of peeling off the silicon oxide film, and a third step of performing heat treatment on the silicon wafer in a hydrogen atmosphere.

Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.

Abstract: The present invention relates to a titanium oxide porous particle for blood purification, which includes a titanium oxide, in which when the titanium oxide porous particle is measured by an electron spin resonance measurement at a temperature of 10 K, a signal at a g value of around 1.96 is present, the signal being divided into two signals representing a component g1 parallel to a axis of symmetry and a component g2 vertical to the axis of symmetry, and a signal at a g value of from 2.003 to 2.004 is not substantially present.

Abstract: Provided are a ceramic-fine-particle producing process making it possible to produce, with ease, ceramic fine particles which have a spherical shape close to a complete round and an excellent mono-dispersibility, and are made only of a solid component of a simple ceramic material without making a fine channel structure complicated, and an apparatus used therein for producing ceramic fine particles. The process includes the step (S100) of feeding a dispersion phase made of an aqueous liquid containing a gelling agent to act upon cooling and a ceramic material into a continuous phase made of an oily liquid containing a surfactant, thereby producing fine droplets; the step (S110) of collecting and cooling the produced fine droplets; the step (S120) of washing the cooled fine droplets; the step (S130) of drying the washed fine droplets; and the step (S140) of firing the dried fine droplets.

Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.

Abstract: A decompression apparatus has an exhaust mechanism for decompressing a vacuum chamber. The exhaust mechanism has a main exhaust passage one end of which is connected to the vacuum chamber and the other end of which is connected to a vacuum pump, a first valve disposed in the main exhaust passage; a slow exhaust passage one end of which is connected to the vacuum chamber directly or via part of the main exhaust passage and the other end of which is connected to the vacuum pump directly or via part of the main exhaust passage, a cylindrical inorganic porous body disposed in the slow exhaust passage so that a gap is formed between the inorganic porous body and the inner surface of the slow exhaust passage, and a second valve disposed in the slow exhaust passage.

Abstract: The present invention provides a compound semiconductor substrate, including: a single-crystal silicon substrate having a crystal face with (111) orientation; a first buffer layer which is formed on the single-crystal silicon substrate and is constituted of an AlxGa1-xN single crystal (0<x?1); a second buffer layer which is formed on the first buffer layer and is composed of a plurality of first unit layers each having a thickness of from 250 nm to 350 nm and constituted of an AlyGa1-yN single crystal (0?y<0.1) and a plurality of second unit layers each having a thickness of from 5 nm to 20 nm and constituted of an AlzGa1-zN single crystal (0.9<z?1), said pluralities of first and second unit layers having been alternately superposed; and a semiconductor device formation region which is formed on the second buffer layer and includes at least one nitride-based semiconductor single-crystal layer.

Abstract: To provide a plane heater, including a carbon wire heating element CW, in which surface arrangement density of the heating element CW in an outer area is denser than that in an inner area. A power supply terminal unit having connection wires for supplying electricity to the heating element CW is arranged in the center on the back side of a silica glass plate-like member 2. Connection wires 4a and 4b connected with the heating element CW in the inner area are connected with the heating element in the inner area in the center of the silica glass plate-like member. Connection wires 3a and 3b connected with the heating element in the outer area are extended from the center of the silica glass plate-like member toward the outer area and connected with the heating element CW in the outer area, without intersecting the heating element CW in the inner area.

Abstract: According to one exemplary embodiment, a single crystal pulling-up apparatus of pulling-up silicon single crystals by a Czochralski method, is provided with: a neck diameter measuring portion which measures a diameter of a grown neck portion; a first compensation portion which outputs a first compensated pulling-up speed for the seed crystals based on a difference between a measured value of the diameter of the neck portion and a target value of the neck portion diameter previously stored; a second compensation portion which outputs a second pulling-up speed while limiting an upper limit of the first pulling-up speed to a first limit value; and a crucible rotation number compensation portion which lowers the number of a rotation of a crucible at least in a period where the upper limit of the first pulling-up speed is limited to the first limit value.

Abstract: The present invention relates to a ceramics composite including an inorganic material which includes: a matrix phase including a translucent ceramics; and a phosphor phase including YAG containing Ce, in which a content of the phosphor phase is from 22% by volume to 55% by volume based on the whole phase including the matrix phase and the phosphor phase, a content of Ce in the YAG is 0.005 to 0.05 in terms of an atomic ratio of Ce to Y (Ce/Y), and the ceramics composite has a thickness in a light outgoing direction of 30 ?m to 200 ?m.

Abstract: The present invention relates to a cell culture support for culturing mesenchymal stem cells, which includes en upper surface including a plurality of wells, in which the upper surface has a root mean square roughness Rq of 100 to 280 nm and a linear density of 1.6 to 10 per 1 ?m length.

Abstract: A planar heater 1 in which a power supply terminal unit 108 which supplies an electric power is arranged on a central portion on a lower surface of a silica glass plate-like member 102. The power supply terminal unit includes small-diameter silica glass tubes 105a and 106a, which contain a connection line which supplies an electric power to a carbon heat generator and a large-diameter silica glass tube 2 which contains the small-diameter silica glass tubes 105a and 106a. A flange portion 2a is formed on a lower end of the large-diameter silica glass tube 2, and a bent portion 2b having different diameters is formed between an upper end of the large-diameter silica glass and the flange portion 2a, and the first heat shielding plates 19, 20 and 21 configured by metal plates or opaque silica glass plates are contained in the large-diameter silica glass tube below the bent portion.

Abstract: The present invention provides a method of manufacturing a silicon single crystal which can more greatly suppress a pinhole formation in the silicon single crystal, which is a method of manufacturing a silicon single crystal by the Czochralski method in which a silicon material to be silicon melt is melted in a furnace body and then a silicon single crystal is pulled up. After melting the silicon material and before the start of pulling up the silicon single crystal, a heater power is set to be higher than that during the step of pulling up the silicon single crystal, and an internal furnace pressure is set as 30 Torr or less, which is lower than that during the step of pulling up the silicon single crystal, the power and pressure being maintained for a predetermined time, and then the step of pulling up the silicon single crystal is carried out.