Abstract: A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.

Abstract: An apparatus is disclosed for remotely monitoring and developing steps in a semiconductor manufacturing process that includes, at least one remote workstation connected via a remote access link to a local workstation, and a test system connected via a link to the local workstation. A method is also disclosed that includes running a semiconductor test system remotely, monitoring the semiconductor test system remotely, and receiving data from the semiconductor test system remotely. Another embodiment includes an apparatus for remotely monitoring and developing steps in a semiconductor manufacturing process. This embodiment includes a plurality of remote workstations each connected via a remote access link to a local workstation, and a test system connected via a link to a local workstation. Security features in this embodiment prevent any one remote workstation from accessing any other remote workstation.

Abstract: A method of verifying test data for testing an integrated circuit device having multiple device time domains includes selecting a virtual tester time domain and, if the cycle duration of the virtual tester time domain is equal to the cycle duration of one of the multiple device time domains, translating the test data for each device time domain other than that one time domain to the virtual tester time domain and otherwise translating the test data for each device time domain to the virtual tester time domain. The translated test data is then applied to a device logic simulator that simulates integrated circuit device.

Abstract: Apparatus for testing semiconductor integrated circuit devices in wafer form includes a test head, a probe card support mechanism attached to the test head for supporting a probe card beneath the test head, a wafer prober for presenting successive wafers to be tested to the test head from beneath the test head, and a lifting mechanism attached to the wafer prober for lifting the test head above the wafer prober. Upon lifting the test head above the wafer prober, the probe card support mechanism can move horizontally relative to the test head between an inserted position in which the probe card support mechanism is positioned to enable the probe card to engage contact elements of the test head and an extended position in which the probe card can be removed from the probe card support mechanism.

Abstract: An analog test instrument used in an apparatus for testing electronic devices has multiple analog modules for supplying test signals to analog pins of a device under test and receiving response signals from the analog pins. The analog modules may be of the same type or of different types. The analog test instrument also has programmable devices that control in an independent manner the triggering, clocking, and generation of the test signals supplied by each of the analog modules, so that test signals of various timings, speeds and waveforms may be generated.

Abstract: A semiconductor integrated circuit tester includes a generally parallelepipedal housing, a main tester board in the housing, and an interface unit incorporating a tester interface that is connected to the main tester board. A support mechanism supports the interface unit in a manner allowing pivotal movement of the interface unit relative to the housing.

Abstract: A single-photon detector includes a superconductor strip biased near its critical current. The superconductor strip provides a discernible output signal upon absorption of a single incident photon. In one example, the superconductor is a strip of NbN (niobium nitride). In another example, the superconductor strip meanders to increase its probability of receiving a photon from a light source. The single-photon detector is suitable for a variety of applications including free-space and satellite communications, quantum communications, quantum cryptography, weak luminescence, and semiconductor device testing.

Abstract: A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a “fail” bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also includes a set of programmable area fail counters, each for counting of the number of memory cells within a separately selected area of the memory's address space. After the test, the computer processes the counts to determine whether it needs to allocate the spare rows and columns and, in some cases, to determine how to allocate the spare rows and columns.

Abstract: A testing method and circuit used to test high-speed communication devices on Automatic Test Equipment—ATE. The method and circuit provide a solution to testing very high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the Device Under Test (DUT) to multiple tester channels which under-sample the streams. The testing method and circuit also allow for the injection of jitter into to the DUT at the output of the DUT. The skipping of data bits inherent in multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test time and improving Bit Error Rate). Moreover the circuit synchronizes different DUTs with the timing of ATE hardware independent of DUT output data. Also, a calibration method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components.

Abstract: Systems and methods consistent with principles of the present invention allow contactless measuring of various kinds of electrical activity within an integrated circuit. The invention can be used for high-bandwidth, at speed testing of various devices on a wafer during the various stages of device processing, or on packaged parts at the end of the manufacturing cycle. Power is applied to the test circuit using conventional mechanical probes or other means, such as CW laser light applied to a photoreceiver provided on the test circuit. The electrical test signal is introduced into the test circuit by stimulating the circuit using a contactless method, such as by directing the output of one or more modelocked lasers onto high-speed receivers on the circuit, or by using a high-speed pulsed diode laser.

Abstract: A plurality of images, including a first image and a second image having a higher resolution than the first image, are aligned by generating an oversampled cross correlation image that corresponds to relative displacements of the first and second images, and, based on the oversampled cross correlation image, determining an offset value that corresponds to a misalignment of the first and second images. The first and second images are aligned to a precision greater than the resolution of the first image, based on the determined offset value. Enhanced results are achieved by performing another iteration of generating an oversampled cross correlation image and determining an offset value for the first and second images. Generating the oversampled cross correlation image may involve generating a cross correlation image that corresponds to relative displacements of the first and second images, and oversampling the cross correlation image to generate the oversampled cross correlation image.

Abstract: Method and apparatus for optically testing (e.g., using a laser beam) an operating integrated circuit (device under test—DUT) that actively control the operating temperature of the DUT. This is chiefly useful with flip-chip packaged ICs. The temperature of the DUT varies with its operating power consumption, and this fluctuation in temperature adversely affects the results obtained during optical probing or other optical testing. Furthermore, the DUT may be damaged if its temperature exceeds design limits. The temperature of the DUT is controlled by thermally contacting the exposed backside surface of the DUT die to a diamond film heat conductor, an associated heat sink structure, and at least one thermoelectric device. The thermoelectric device is controlled by a temperature sensor proximal to the DUT. By controlling the amount and direction of the electrical current supplied to the thermoelectric device in response to the sensed temperature, the temperature of the DUT is maintained.

Abstract: An algorithmic pattern generator for generating an output vector on each pulse of a clock signal includes a vector memory for storing a vector and an accompanying repeat number at each of several addresses. On each of N consecutive clock signal pulses, a repeat processor appends an instance of a vector read out of the vector memory to the pattern generator's output vector sequence. An instruction processor causes the instruction memory to read out instructions and responds to each instruction by telling the instruction processor to signal the address counter to supply the starting address to the vector memory and to thereafter periodically increment the starting address for M consecutive clock signal cycles. When appending N instances of each vector to the pattern generator output sequence, the repeat processor inhibits the address counter from incrementing its output address for N−1 cock signal cycles.

Abstract: A landing system is provided for accurate placing of collection optics in a microscope. In one example, a solid immersion lens (SIL) is used for light collection, and the landing system is operated to place the SIL in contact with an IC. A proximity sensor is used for determining the SIL's position with respect to the IC. The proximity sensor is attached to a z-motion stage. During the placement procedure, the navigation is performed in steps and at each step the compression of the SIL is measured relative to its uncompressed state. When a measured compression exceeds a preset threshold, a SIL landing is recognized. In one example, after a landing is recognized, a further compression is imparted to the SIL in order to place the SIL in a focusing distance to the objective lens.

Abstract: A micro-machining process that includes etching a substrate having copper overlying a dielectric layer to a charged particle beam in the presence of an etch assisting agent. The etch assisting agent is selected from the group consisting of ammonia, acetic acid, thiolacetic acid, and combinations thereof.

Abstract: PICA probe system methods and apparatus are described, including methods and apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted and a fine measurement capability in which time between boundaries is interpolated using a voltage ramp.

Abstract: A single photon detector includes a superconductor strip biased near its critical current. The superconductor strip provides a discernible output signal upon absorption of a single incident photon. In one example, the superconductor is a strip of NbN (niobium nitride). In another example, the superconductor strip meanders to increase its probability of receiving a photon from a light source. The single-photon detector is suitable for a variety of applications including free-space and satellite communications, quantum communications, quantum cryptography, weak luminescence, and semiconductor device testing.

Abstract: A method for manufacturing an improved APD structure and an improved manner of operating APD's particularly beneficial for a single photon detection applications are provided. An APD is provided having an absorption region, a control region, and a multiplication region, wherein the multiplication region has a k value of approximately 1. In one example the multiplication region comprises a doped InP layer. The field control layer is designed so as to produce a reduction of electric field that is equal to the multiplication region's breakdown electric field, plus or minus 5V/&mgr;m. The method comprises applying a potential across the APD so as to induce an electric field across the multiplication region that exceeds the breakdown field; while having the control region shield the absorption region to prevent excessive noise.

Abstract: A pin card for mounting in a test head of a semiconducter integrated circuit tester to implement test channels of the tester includes contact pins connected to terminals of respective test channels. Each contact pin has a free end for engaging a load board. A conductive switch element is displaceable between a first position, in which the switch element is electrically isolated from one or more of the contact pins, and a second position, in which the switch element is in electrically conductive contact with one or more of the contact pins.

Abstract: A bi-convex solid immersion lens is disclosed. Unlike conventional plano-convex solid immersion lenses having a flat bottom surface, the disclosed lens has a convex bottom surface. The radius of curvature of the bottom surface is smaller than that of the object to be inspected. This construction allows for a more accurate determination of the location of the inspected feature, and enhances coupling of light between the immersion lens and the inspected object. The disclosed lens is particularly useful for use in microscope for inspection of semiconductor devices and, especially flip-chip (or chip scale) packaged devices. The immersion lens can also be incorporated in a read or read/write head of optical memory media.