Patents Assigned to Cree Research, Inc.
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Patent number: 6281521Abstract: Silicon carbide channel semiconductor devices are provided which eliminate the insulator of the gate by utilizing a semiconductor gate layer and buried base regions to create a “pinched off” gate region when no bias is applied to the gate. In particular embodiments of the present invention, the semiconductor devices include a silicon carbide drift layer of a first conductivity type, the silicon carbide drift layer having a first face and having a channel region therein. A buried base region of a second conductivity type semiconductor material is provided in the silicon carbide drift layer so as to define the channel region. A gate layer of a second conductivity type semiconductor material is formed on the first face of the silicon carbide drift layer adjacent the channel region of the silicon carbide drift layer. A gate contact may also be formed on the gate layer. Both transistors and thyristors may be provided.Type: GrantFiled: July 9, 1998Date of Patent: August 28, 2001Assignee: Cree Research Inc.Inventor: Ranbir Singh
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Patent number: 6218254Abstract: A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface.Type: GrantFiled: September 22, 1999Date of Patent: April 17, 2001Assignee: Cree Research, Inc.Inventors: Ranbir Singh, Anant K. Agarwal, Sei-Hyung Ryu
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Patent number: 6121633Abstract: A MOS bipolar transistor is provide which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer a p-type base layer. Preferably the base layer is formed by epitaxial growth and formed as a mesa. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also included are means for converting electron current flowing between the source and the drain into hole current for injection into the p-type base layer. Means for reducing field crowding associated with an insulating layer of said nMOSFET may also be provided.Type: GrantFiled: May 21, 1998Date of Patent: September 19, 2000Assignee: Cree Research, Inc.Inventors: Ranbir Singh, John W. Palmour
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Patent number: 6107142Abstract: Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate through an opening in a mask, to form a deep p-type implant. N-type dopants are implanted into the silicon carbide substrates through the same opening in the mask, to form a shallow n-type implant relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivity, while the n-type dopant having low diffusivity remains relatively fixed.Type: GrantFiled: June 8, 1998Date of Patent: August 22, 2000Assignee: Cree Research, Inc.Inventors: Alexander Suvorov, John W. Palmour, Ranbir Singh
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Patent number: 6025289Abstract: Large single crystals of silicon carbide are grown in a furnace sublimation system. The crystals are grown with compensating levels of p-type and n-type dopants (i.e., roughly equal levels of the two dopants) in order to produce a crystal that is essentially colorless. The crystal may be cut and fashioned into synthetic gemstones having extraordinary toughness and hardness, and a brilliance meeting or exceeding that of diamond.Type: GrantFiled: December 4, 1997Date of Patent: February 15, 2000Assignee: Cree Research, Inc.Inventors: Calvin H. Carter, Valeri F. Tsvetkov, Robert C. Glass
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Patent number: 6011279Abstract: A field controlled bipolar switch having a bulk single crystal silicon carbide substrate of a first conductivity type having an upper surface and a lower surface. A first epitaxial layer of a second conductivity type silicon carbide is formed upon the upper surface of the substrate. A second epitaxial layer of the second conductivity type silicon carbide is formed on the first epitaxial layer of silicon carbide. A plurality of regions of a third conductivity type silicon carbide are formed in the second epitaxial layer to form a gate grid in the second epitaxial layer. A third epitaxial layer of the second conductivity type silicon carbide is formed on the second epitaxial layer and a fourth epitaxial layer of the second conductivity type silicon carbide is formed upon the third epitaxial layer. The fourth epitaxial layer has a higher carrier concentration than is present in the first, second and third epitaxial layers.Type: GrantFiled: April 30, 1997Date of Patent: January 4, 2000Assignee: Cree Research, Inc.Inventors: Ranbir Singh, John W. Palmour
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Patent number: 5972801Abstract: A method is disclosed for obtaining improved oxide layers and resulting improved performance from oxide based devices. The method comprises exposing an oxide layer on a silicon carbide layer to an oxidizing source gas at a temperature below the temperature at which SiC would begin to oxidize at a significant rate, while high enough to enable the oxidizing source gas to diffuse into the oxide layer, and while avoiding any substantial additional oxidation of the silicon carbide, and for a time sufficient to densify the oxide layer and improve the interface between the oxide layer and the silicon carbide layer.Type: GrantFiled: November 8, 1995Date of Patent: October 26, 1999Assignee: Cree Research, Inc.Inventors: Lori A. Lipkin, David B. Slater, Jr., John W. Palmour
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Patent number: 5969378Abstract: A MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and p-type base layer. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also provide are means for converting electrons flowing between the source and the drain into holes for injection into the p-type base layer. Unit cells and methods of forming such devices are also provided.Type: GrantFiled: July 10, 1997Date of Patent: October 19, 1999Assignee: Cree Research, Inc.Inventor: Ranbir Singh
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Patent number: 5923946Abstract: A method is disclosed for recovering surface-ready silicon carbide substrates from heteroepitaxial structures of Group III nitrides on silicon carbide substrates. The method comprises subjecting a Group III nitride epitaxial layer on a silicon carbide substrate to a stress that sufficiently increases the number of dislocations in the epitaxial layer to make the epitaxial layer subject to attack and dissolution in a mineral acid, but that otherwise does not affect the silicon carbide substrate, and thereafter contacting the epitaxial layer with a mineral acid to remove the Group III nitride while leaving the silicon carbide substrate unaffected.Type: GrantFiled: April 17, 1997Date of Patent: July 13, 1999Assignee: Cree Research, Inc.Inventor: Gerald H. Negley
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Patent number: 5912477Abstract: Light emitting diodes are disclosed which have increased external efficiency and are formed from silicon carbide substrates. Diodes are produced by a method which includes directing a beam of laser light at one surface of a portion of silicon carbide, and which the laser light is sufficient to vaporize the silicon carbide that it strikes to thereby define a cut in the silicon carbide portion; and then dry etching the silicon carbide portion to remove by-products generated when the laser light cuts the silicon carbide portion. The resulting diode structure includes reticulate patterned sidewalls that promote increased light emission efficiency.Type: GrantFiled: May 20, 1997Date of Patent: June 15, 1999Assignee: Cree Research, Inc.Inventor: Gerald H. Negley
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Patent number: 5838706Abstract: A Group III nitride laser structure is disclosed with an active layer that includes at least one layer of a Group III nitride or an alloy of silicon carbide with a Group III nitride, a silicon carbide substrate, and a buffer layer between the active layer and the silicon carbide substrate. The buffer layer is selected from the group consisting of gallium nitride, aluminum nitride, indium nitride, ternary Group III nitrides having the formula A.sub.x B.sub.1-x N, where A and B are Group III elements and where x is zero, one, or a fraction between zero and one, and alloys of silicon carbide with such ternary Group III nitrides. In preferred embodiments, the laser structure includes a strain-minimizing contact layer above the active layer that has a lattice constant substantially the same as the buffer layer.Type: GrantFiled: November 19, 1996Date of Patent: November 17, 1998Assignee: Cree Research, Inc.Inventors: John Adam Edmond, Gary E. Bulman, Hua-Shuang Kong
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Patent number: 5831288Abstract: A silicon carbide (SiC) metal-insulator semiconductor field effect transistor having a u-shaped gate trench and an n-type SiC drift layer is provided. A p-type region is formed in the SiC drift layer and extends below the bottom of the u-shaped gate trench to prevent field crowding at the corner of the gate trench. A unit cell of a metal-insulator semiconductor transistor is provided having a bulk single crystal SiC substrate of n-type conductivity SiC, a first epitaxial layer of n-type SiC and a second epitaxial layer of p-type SiC. First and second trenches extend downward through the second epitaxial layer and into the first epitaxial layer with a region of n-type SiC between the trenches. An insulator layer is formed in the first trench with the upper surface of the insulator on the bottom of the trench below the second epitaxial layer. A region of p-type SiC is formed in the first epitaxial layer below the second trench.Type: GrantFiled: September 29, 1997Date of Patent: November 3, 1998Assignee: Cree Research, Inc.Inventors: Ranbir Singh, John W. Palmour
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Patent number: 5812105Abstract: A method and apparatus for driving a light emitting diode (LED) display having a matrix of LEDs of different colors wherein different color LEDs of the matrix are commonly connected so that a voltage applied to one LED of the commonly connected LEDs is applied to all of the commonly connected LEDs. Different voltages are applied to the commonly connected different color LEDs in the matrix of LEDs. A drive circuit may have commonly connected drivers which multiplex voltages to an array of commonly connected LEDs such that different voltages may be applied to LEDs having different operating voltages. An LED display is also provided.Type: GrantFiled: June 10, 1996Date of Patent: September 22, 1998Assignee: Cree Research, Inc.Inventor: Antony Paul Van de Ven
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Patent number: 5776837Abstract: A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.Type: GrantFiled: November 19, 1996Date of Patent: July 7, 1998Assignee: Cree Research, Inc.Inventor: John W. Palmour
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Patent number: 5739554Abstract: A double heterostructure for a light emitting diode comprises a layer of aluminum gallium nitride having a first conductivity type; a layer of aluminum gallium nitride having the opposite conductivity type; and an active layer of gallium nitride between the aluminum gallium nitride layers, in which the gallium nitride layer is co-doped with both a Group II acceptor and a Group IV donor, with one of the dopants being present in an amount sufficient to give the gallium nitride layer a net conductivity type, so that the active layer forms a p-n junction with the adjacent layer of aluminum gallium nitride having the opposite conductivity type.Type: GrantFiled: May 8, 1995Date of Patent: April 14, 1998Assignee: Cree Research, Inc.Inventors: John A. Edmond, Hua-Shuang Kong
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Patent number: 5724062Abstract: A high resolution, high brightness, full color display is provided having a liquid crystal pixel selectably addressable during a predetermined time period, a set of at least one red, one green, and one blue color light emitting diodes positioned adjacent the liquid crystal pixel for emitting light through the liquid crystal pixel, and means connected to the liquid crystal pixel for addressing the liquid crystal pixel a plurality of times during the predetermined time period for each color so as to provide persistence when changes in color are perceived by the human eye.Type: GrantFiled: September 21, 1994Date of Patent: March 3, 1998Assignee: Cree Research, Inc.Inventor: C. Eric Hunter
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Patent number: 5718760Abstract: Large single crystals of silicon carbide are grown in a furnace sublimation system. The crystals are grown with compensating levels of p-type and n-type dopants (i.e., roughly equal to levels of the two dopants) in order to produce a crystal that is essentially colorless. The crystal may be cut and fashioned into synthetic gemstones having extraordinary toughness and hardness, and a brilliance meeting or exceeding that of diamond.Type: GrantFiled: February 5, 1996Date of Patent: February 17, 1998Assignee: Cree Research, Inc.Inventors: Calvin H. Carter, Valeri F. Tsvetkov, Robert C. Glass
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Patent number: 5719409Abstract: A silicon carbide (SIC) metal-insulator semiconductor field effect transistor having a u-shaped gate trench and an n-type SiC drift layer is provided. A p-type region is formed in the SiC drift layer and extends below the bottom of the u-shaped gate trench to prevent field crowding at the corner of the gate trench. A unit cell of a metal-insulator semiconductor transistor is provided having a bulk single crystal SiC substrate of n-type conductivity SiC, a first epitaxial layer of n-type SiC and a second epitaxial layer of p-type SiC. First and second trenches extend downward through the second epitaxial layer and into the first epitaxial layer with a region of n-type SiC between the trenches. An insulator layer is formed in the first trench with the upper surface of the insulator on the bottom of the trench below the second epitaxial layer. A region of p-type SiC is formed in the first epitaxial layer below the second trench.Type: GrantFiled: June 6, 1996Date of Patent: February 17, 1998Assignee: Cree Research, Inc.Inventors: Ranbir Singh, John W. Palmour
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Patent number: 5686737Abstract: A metal-semiconductor field-effect-transistor (MESFET) is disclosed that exhibits reduced source resistance and higher operating frequencies. The MESFET comprises an epitaxial layer of silicon carbide, and a gate trench in the epitaxial layer that exposes a silicon carbide gate surface between two respective trench edges. A gate contact is made to the gate surface, and with the trench further defines the source and drain regions of the transistor. Respective ohmic metal layers form ohmic contacts on the source and drain regions of the epitaxial layer, and the edges of the metal layers at the trench are specifically aligned with the edges of the epitaxial layer at the trench.Type: GrantFiled: September 16, 1994Date of Patent: November 11, 1997Assignee: Cree Research, Inc.Inventor: Scott T. Allen
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Patent number: 5679153Abstract: A method is disclosed for producing epitaxial layers of silicon carbide that are substantially free of micropipe defects. The method comprises growing an epitaxial layer of silicon carbide on a silicon carbide substrate by liquid phase epitaxy from a melt of silicon carbide in silicon and an element that enhances the solubility of silicon carbide in the melt. The atomic percentage of that element predominates over the atomic percentage of silicon in the melt. Micropipe defects propagated by the substrate into the epitaxial layer are closed by continuing to grow the epitaxial layer under the proper conditions until the epitaxial layer has a thickness at which micropipe defects present in the substrate are substantially no longer reproduced in the epitaxial layer, and the number of micropipe defects in the epitaxial layer is substantially reduced.Type: GrantFiled: November 30, 1994Date of Patent: October 21, 1997Assignee: Cree Research, Inc.Inventors: Vladimir A. Dmitriev, Svetlana V. Rendakova, Vladimir A. Ivantsov, Calvin H. Carter, Jr.