Abstract: An apparatus includes a circuit including multiple magnetic tunnel junctions, the circuit configured to convert a quadrature modulated magnetic field to a quadrature modulated electrical signal, each magnetic tunnel junction including a storage layer having a storage magnetization and a sense layer having a sense magnetization, each magnetic tunnel junction being configured such that the sense magnetization and impedance of each magnetic tunnel junction vary in response to the quadrature modulated magnetic field. The apparatus further includes a module configured to demodulate the quadrature modulated electrical signal to recover a signal encoded in the quadrature modulated magnetic field.

Abstract: An apparatus includes circuits including a first circuit and a second circuit, each circuit including subarrays of magnetic tunnel junctions, where: (1) the magnetic tunnel junctions in each subarray are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel; and (2) the subarrays are connected in series. The apparatus further comprises a field line configured to generate a first magnetic field for configuring an operating point of the first circuit based on a current flow through the field line, where the impedance of a subset of the plurality of rows in each subarray of magnetic tunnel junctions included in the first circuit is configured based on the first magnetic field.

Abstract: An apparatus includes circuits including a first circuit and a second circuit, each circuit including subarrays of magnetic tunnel junctions, where: (1) the magnetic tunnel junctions in each subarray are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel; and the subarrays are connected in series. The apparatus further comprises a field line configured to generate a first magnetic field for configuring an operating point of the first circuit based on a current flow through the field line, wherein impedance of one or more of the magnetic tunnel junctions in each of the plurality of rows of each subarray of magnetic tunnel junctions included in the first circuit is configured based on the first magnetic field.

Abstract: An apparatus includes circuits and a module configured to determine an external magnetic field based on a parameter of each circuit. Each circuit includes an array of magnetic tunnel junctions partitioned into subarrays. The magnetic tunnel junctions in each subarray are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel. The subarrays are connected in series. Each magnetic tunnel junction includes a storage layer having a storage magnetization and a sense layer having a sense magnetization. Each magnetic tunnel junction is configured such that the sense magnetization and impedance of each magnetic tunnel junction vary in response to an external magnetic field. The parameter of each circuit varies based on a combined impedance of the multiple magnetic tunnel junctions. The module is implemented in at least one of a memory or a processing device.

Abstract: Self-referenced magnetic random access memory (MRAM) cell including a magnetic tunnel junction including a sense layer; a storage layer having a storage magnetization; a tunnel barrier layer between the sense and the storage layers; and an antiferromagnetic layer exchange-coupling the storage layer such that the storage magnetization can be pinned when the antiferromagnetic layer is below a critical temperature and freely varied when the antiferromagnetic layer is heated at or above the critical temperature. The sense layer includes a first sense layer having a first sense magnetization, a second sense layer having a second sense magnetization and spacer layer between the first and second sense layers. The MRAM cell can be read with low power consumption.

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

Abstract: An apparatus includes an elongated strap with a first platform and a second platform linked by a connector that is substantially narrower than the first platform and the second platform, where the first platform and the second platform are each configured to receive a stress sensitive device.

Abstract: A check engine includes comparators, where each comparator has flash cells. Each comparator is configured to store at least one reference bit included in a set of reference bits defining a first pattern. Each comparator also includes an input for presenting at least one target bit included in a set of target bits defining a second pattern. Each comparator is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the comparators are combined to produce a combined output that is compared to a reference signal to determine whether there is a match between the first pattern and the second pattern.

Abstract: An apparatus has magnetic logic units a logic circuit configured to receive a serial input bit stream at an input node. Individual bits of data from the serial input bit stream are serially written into individual magnetic logic units without buffering the serial input bit stream between the input node and the individual magnetic logic units. Individual bits of data from individual magnetic logic units are serially read to produce a serial output bit stream on an output node without buffering the serial output bit stream between the individual magnetic logic units and the output node.

Abstract: Magnetic element including a first magnetic layer having a first magnetization; a second magnetic layer having a second magnetization; a tunnel barrier layer between the first and the second magnetic layers; and an antiferromagnetic layer exchanged coupling the second magnetic layer such that the second magnetization is pinned below a critical temperature of the antiferromagnetic layer, and can be freely varied when the antiferromagnetic layer is heated above that critical temperature. The magnetic element also includes an oxygen gettering layer between the second magnetic layer and the antiferromagnetic layer, or within the second magnetic layer. The magnetic element has reduced insertion of oxygen atoms in the antiferromagnetic layer and possibly reduced diffusion of manganese in the second magnetic layer resulting in an enhanced exchange bias and/or enhanced resistance to temperature cycles and improved life-time.

Abstract: MRAM cell comprising a magnetic tunnel junction comprising a storage layer having a net storage magnetization being adjustable when the magnetic tunnel junction is at a high temperature threshold and being pinned at a low temperature threshold; a sense layer having a reversible sense magnetization; and a tunnel barrier layer between the sense and storage layers; at least one of the storage and sense layer comprising a ferrimagnetic 3d-4f amorphous alloy material comprising a sub-lattice of 3d transition metals atoms providing a first magnetization and a sub-lattice of 4f rare-earth atoms providing a second magnetization, such that at a compensation temperature of said at least one of the storage layer and the sense layer, the first magnetization and the second magnetization are substantially equal. The disclosed MRAM cell can be written and read using a small writing and reading field, respectively.

Abstract: Self-reference-based MRAM element including: first and second magnetic tunnel junctions, each having a magnetoresistance that can be varied; and a field line for passing a field current to vary the magnetoresistance of the first and second magnetic tunnel junctions. The field line includes a first branch and a second branch each branch including cladding. The first branch is arranged for passing a first portion of the field current to selectively vary the magnetoresistance of the first magnetic tunnel junction, and the second branch is electrically connected in parallel with the first branch and arranged for passing a second portion of the field current to selectively vary the magnetoresistance of the second magnetic tunnel junction. The self-referenced MRAM element and an MRAM device including corresponding MRAM elements can use a reduced field current.

Abstract: A magnetic logic unit (MLU) cell includes a first and second magnetic tunnel junction, each including a first magnetic layer having a first magnetization, a second magnetic layer having a second magnetization, and a barrier layer; and a field line for passing a field current such as to generate an external magnetic field adapted to adjust the first magnetization. The first and second magnetic layers and the barrier layer are arranged such that the first magnetization is magnetically coupled antiparallel with the second magnetization through the barrier layer. The MLU cell also includes a biasing device arranged for applying a static biasing magnetic field oriented substantially parallel to the external magnetic field such as to orient the first magnetization at about 90° relative to the second magnetization, the first and second magnetizations being oriented symmetrically relative to the direction of the external magnetic field.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on an analog input to the circuit. Each MTJ is electrically connected to a first output terminal and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of each of the MTJs varies based on the magnetic field. The circuit is configured to generate an analog output based on the output of at least one of the first and the second output terminal.

Abstract: A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on a first analog input to the circuit. Each MTJ is electrically connected to a first and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of the MTJs varies based on the magnetic field. The circuit is configured to mix the first analog input and a second analog input to generate an analog output based on the output of the second output terminal.

Abstract: Method for writing to a MRAM cell including a magnetic tunnel junction including a first and second ferromagnetic layer, and a tunnel barrier layer; and a bipolar transistor in electrical connection with one end of the magnetic tunnel junction, the bipolar transistor being arranged for controlling the passing and polarity of a heating current in the magnetic tunnel junction. The method includes a sequence of writing steps, each writing step including passing the heating current in the magnetic tunnel junction such as to heat it to a high temperature threshold; and once the magnetic tunnel junction has reached the high temperature threshold, adjusting a second magnetization of the second ferromagnetic layer for writing a write data; wherein during one of the writing steps, the polarity of the heating current is reversed from one during the subsequent writing step. The method allows for an increased lifespan of the MRAM cell.

Abstract: A manufacturing method to form a memory device includes forming a hard mask on a magnetic stack. A first magnetic stack etch is performed to form exposed magnetic layers. A liner is applied to the exposed magnetic layers to form protected magnetic layers. A second magnetic stack etch forms a magnetic random access memory (MRAM) cell, where the liner prevents shunting between the protected magnetic layers.

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract: The present disclosure concerns a MRAM cell comprising a first tunnel barrier layer comprised between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer comprised between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.