Abstract: A Successive Approximation Analog-to-Digital Converter (SAR_ADC) and method of operating the same are provided. Generally, the SAR_ADC includes a comparator having a first input to receive an input voltage (VIN), and a second input coupled to a n-bit capacitive digital-to-analog converter (DAC) to receive a voltage (VDAC), a Successive Approximation Register (SAR) coupled to a comparator output to provide n digital control signals to the DAC, and to store and output an n-bit binary-number approximating VIN, and a reference buffer to provide a voltage (VREF) to the DAC. The DAC sequentially drives each capacitance beginning with a most significant bit towards VREF, while the comparator compares the resulting VDAC to VIN, and the SAR sets or clears a current bit represented by the capacitance driven. The reference buffer includes adaptive power tuning to dynamically tune a drive-strength of the reference buffer based on the current bit.

Abstract: Measured signal data, detected by a sensor array of a device, is used to create a generated representation from the measured signal data. The generated representation is compared with a measured representation of the measured signal data to create a correlation coefficient corresponding to a correlation between the generated representation and the measured representation of the measured signal data. A hover event is detected for the device if the correlation coefficient exceeds a first threshold. If the correlation coefficient does not exceed the first threshold, then the measured signal data is determined to not be indicative of a hover event.

Abstract: A device includes a transmitter to generate a sampled stream of data for a packet at a first sample rate. A data re-sampling circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo-clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate, and a time-shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A comparator circuit uses the re-sampled data values to match the re-sampled data values to a corresponding data value detected in the data pattern in the frame delimiter. A timing logic uses the plurality of re-timer values and the location of the marker in the data pattern in a timing calculation.

Abstract: Systems, methods, and devices enhance management of components used in data converters. Methods include receiving an input at a data converter comprising a digital to analog converter (DAC), the digital to analog converter comprising a plurality of sensing elements, and performing, using the DAC, a first conversion operation based on the input and a first set of the plurality of sensing elements identified by a first pointer value. Methods also include determining a pointer increment value based, at least in part, on an output of the first conversion operation and a hysteresis threshold value, the pointer increment value being used to determine an amount by which the first pointer value is incremented, the hysteresis threshold value identifying a threshold for determination of the pointer increment value.

Abstract: Secondary side peak current control mode flyback converters are described. In one embodiment, an apparatus includes a flyback converter including a flyback transformer and a signal transformer, a primary side including a primary-side controller coupled to a power switch, the flyback transformer and the signal transformer, and a secondary side including a secondary-side controller coupled to the flyback transformer and the signal transformer. The secondary-side controller is configured at least to operate in a current control mode to cause a pulse width modulation (PWM) signal to be generated based on a set of parameters to control operation of the primary-side controller.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a method is provided. The method includes connecting a first programmable electrode interface to one of a first working electrode, a control electrode, a reference electrode, or a guard electrode of an electrochemical cell in a first configuration, and connecting the first programmable electrode interface to a different one of the first working electrode, the control electrode, the reference electrode, or the guard electrode in a second configuration.

Abstract: Systems and methods for translation and transmission of video and audio data over a first-in-first-out interface (FIFO) in a field programmable gate array (FPGA) are provided. The method includes receiving audio and video data including a number of video frames, each with a plurality of video lines separated by a line blanking interval. A first video line is translated and transmitted to a packet-based network through the FIFO in the FPGA while concurrently buffering the audio data in an audio buffer in the FPGA. Next, at least a portion of the audio data in the audio buffer is transmitted to the packet-based network through the FIFO during the line blanking interval separating the first video line from a second video line. Where video frames are separated by frame blanking intervals the method further includes transmitting through the FIFO any data remaining in the buffer after the preceding line blanking interval.

Abstract: Implementations disclosed describe methods and systems to perform the methods of deploying and executing machine learning models on target-specific computational platforms. Optimization techniques include but are not limited to alignment of kernel operations with hardware instructions of a target processing device, reduction of kernel dimensions near boundaries of data, efficient reuse of a small number of memory components during neural network operations, run-time quantization of data and neural network parameters, and other methods.

Abstract: Controlling an active clamp field effect transistor (FET) and a primary-side FET in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET and the primary-side FET across a same galvanic isolation barrier.

Abstract: Systems, methods, and devices provide low-power wakeup operations for wireless devices. Methods include receiving an audio signal from a first wireless device at a second wireless device via an audio transducer, the audio signal including a plurality of encoded data values, and determining, using a processing device of the second wireless device, if the received audio signal includes a valid wakeup code. Methods also include transitioning a transceiver of the second wireless device from a sleep mode to a wake mode in response to determining that the audio signal includes a valid wakeup signal.

Abstract: A current-sink buffer is provided including a differential amplifier having a closed first-loop to provide a buffered output voltage, and a closed second-loop to sink transients in a load current of an output to ground. The first-loop includes a first transistor with a gate coupled to a reference-voltage, and a source coupled to a current-source; a second transistor with a gate coupled to a drain and the output, and a source coupled to the source of the first transistor; a first current-sink through which a drain of the first transistor is coupled to ground; and a second current-sink through which the second transistor drain is coupled to ground. The second-loop includes a third transistor with a grounded source, a drain coupled to the second transistor drain, and a gate coupled to the first transistor drain, and a capacitor coupled between the gate and drain of the third transistor.

Abstract: A floating-rail reference generator and method of operating the same are provided. Generally, the generator includes a tracking current source coupled in series with a current scaling resistor between an input voltage (VBAT) and ground. The tracking current source is operable to receive a reference voltage and couple a tracking current through the resistor to produce a floating-rail reference voltage (VSSHV_REF) at an output between the tracking current source and scaling resistor, wherein: VSSHV_REF=((VBAT-VGS)/k)·1/R·k·R, where VGS is a desired constant potential difference between VBAT and VSSHV_REF, k is a voltage scaling ratio, and R is a resistance of the current scaling resistor. In some embodiments, the tracking current source includes a transistor coupled between VBAT and the output, and controlled by a differential amplifier.

Abstract: A single-rail switching regulator and method are provided. The switching regulator includes a split-rail reference generator coupled between a battery voltage (VBAT) and ground, and including a floating-rail generator to generate a floating-rail reference voltage (VSSHV_REF), a fixed-rail generator to generate a fixed-rail reference voltage (VDD_REF), a current-sinking (I-sink) buffer to receive VSSHV_REF and generate a floating-rail voltage on a floating-rail to power logic devices formed on an IC with the switching regulator, and a high-side switching transistor including a source and drain coupled between VBAT and ground, and a gate coupled to the floating-rail. The floating-rail reference generator is operable to generate a VSSHV_REF equal to VBAT?1.8V for VBAT between 1.8 and 4.8V, and 0V for VBAT less than 1.8V. The switching regulator further includes a low drop out regulator operable to receive VDD_REF and power digital devices formed on the IC using a fixed voltage.

Abstract: A floating-rail voltage generator and method are provided for use in a switched regulator. Generally, the generator includes a floating-rail reference generator, a current-sinking buffer and a current-sink. The reference generator is operable to generate a reference voltage (VSSHV_REF) equal to an input voltage (VBAT) minus 1.8 V for VBAT between 1.8V and 4.8V, and equal to 0V for VBAT less than 1.8V. The buffer is coupled between VBAT and ground, and operable to receive the VSSHV_REF and generate a continuous floating-rail voltage (VSSHV) on a floating-rail for VBAT between 1.6V and 4.8V. The current-sink is operable to receive VSSHV_REF and VSSHV, and to turn on a current sinking switch coupled between the floating-rail and ground by setting a set-reset latch having a latch output coupled to a gate of the current sinking switch when a transient load current signal is received from a load coupled to the floating-rail.

Abstract: Techniques are disclosed for a low-power and low-complexity speech onset detector (SOD) that uses a fractional-band filter structure and spectral subtraction technique to derive sub-band energy profiles to detect the onset of speech in the presence of noise. The SOD derives the sub-band energy profiles by filtering and down-sampling a full-band input audio signal using the fractional-bandwidth filter structure, which may be a low-pass filter with a cut-off frequency that is a fraction of the full bandwidth of the input signal. The SOD flexibly estimates the average noise energy across frames and the current frame speech energy in each sub-band to track noise and speech energy levels across the frames for each of the sub-bands to determine one or more band thresholds used to detect active speech. The sub-band energy profiles leverage any separation in frequency between noise and speech to detect the onset of speech in a target signal.

Abstract: Systems, methods, and devices provide sampling for data converters. Methods include receiving a voltage from a voltage source, and identifying transconductance parameters and resistance parameters associated with a data converter, the transconductance parameters identifying a transconductance of the data converter. Methods also include selecting a resistor from a plurality of dynamically selectable resistors based on the resistance parameters, generating, using a programmable gain amplifier, a current based, at least in part, on the selected resistor and the received voltage, and providing the current to the data converter.

Abstract: A wireless device includes a transmitter and logic at least one of coupled to or integrated within the transmitter. The logic generates a frequency domain artifact within a portion of a packet to be transmitted during a round trip timing estimation of an enclosure having a receiver. The logic causes a frequency of samples of bit patterns of the portion of the packet to be modified based on the frequency domain artifact before the transmitter transmits the packet to the receiver.

Abstract: An example method of estimating the angular resolution of antenna array comprises: receiving a plurality of values of magnitude and phase of a radio frequency (RF) signal for each antenna element of a plurality of antenna elements comprised by an antenna array; performing, by a machine learning model, a feature extraction operation to transform the plurality of values of magnitude and phase into a plurality of data points in a reduced-dimension space; clustering, by the machine learning model, the plurality of data points into a plurality of clusters; and computing, based on the clustered data points, an angular resolution value for the antenna array.

Abstract: Systems, methods, and devices provide low-power-low-latency communication between wireless devices. Methods include determining, using a processing device, state information identifying a state of a first wireless device, and determining, using the processing device, that a data packet should be sent to a second wireless device based on an identified change in the state information. Methods may further include generating, using the processing device, a data packet for transmission from the first wireless device to the second wireless device via an isochronous wireless channel, wherein the data packet is configured to include the state information identifying the change.

Abstract: Disclosed are methods and systems for a Bluetooth Low Energy (BLE) receiver to reduce the number of retransmission of packets needed to receive an error free packet so as to improve channel throughput. Techniques to reduce the number of retransmissions include a combination of processing of the header of the received packets to increase the number of corrupted packets available for reconstructing the original payload and bit error correction (BEC) of the payload of the corrupted packets. Header processing may include making available for payload reconstruction a packet whose received access address differs by no more than 1-bit from an assigned address of the receiver provided at least one of the corrupted packets used in the reconstruction contains an error-free access address. Header processing may also include using a prior error-free decoded length of the packet to aid in the determination of the length field of a current packet.