Abstract: A first step of a calibration procedure is be performed to obtain a first set of voltage measurements by causing each mode switch of a first set of mode switches of a voltage management subsystem to be placed in a first position and each mode switch of a second set of mode switches of the voltage management subsystem to be placed in a second position. Each mode switch is included within a channel of the voltage management subsystem. A second step of the calibration procedure is performed to obtain a second set of voltage measurements by causing each mode switch of the first set of mode switches to be placed in the second position and each mode switch of the second set of mode switches to be placed in the first position.

Abstract: A low-dropout (LDO) regulator includes a voltage reference node and a one-stage differential amplifier coupled to the voltage reference node. The one-stage differential amplifier includes: a differential pair of NMOS transistors; a mirroring load comprising a first current source and a PMOS transistor; a direct feed-forward (DFF) loop formed by the PMOS transistor and its parasitic gate-to-drain capacitance during a load transient; and an indirect regulation feedback (IRF) loop formed by the differential pair of NMOS transistors, a resistor, and the PMOS transistor to provide direct current (DC) voltage regulation.

Abstract: A Universal Serial Bus (USB) controller including a Vconn switch having a current controlled architecture, and method for operating the same, are described. In an example embodiment, the Vconn switch includes first and second transistors coupled in series between a Vconn terminal and a communication channel (CC) terminal, a replica switch coupled to the Vconn terminal, a replica current generator coupled to the replica switch, and a resistance control module coupled to the replica current generator. The replica current generator is operable to match a current through the replica switch to the current supplied to the CC terminal through the first and second transistors. The resistance control module is operable to use a digital output of a current inverter to control an in-rush current to the CC terminal.

Abstract: Implementations disclosed describe methods and systems to perform the methods of deploying and executing machine learning models on target-specific computational platforms. Optimization techniques include but are not limited to alignment of kernel operations with hardware instructions of a target processing device, reduction of kernel dimensions near boundaries of data, efficient reuse of a small number of memory components during neural network operations, run-time quantization of data and neural network parameters, and other methods.

Abstract: The embodiments described herein are directed at techniques to sharing a transmission medium in a Bluetooth transceiver/WLAN transceiver combination device. A first device may receive a request from a second device to use the wireless transmission medium. The second device may also transmit timing data to the first device. The first device may determine a period of time to allow the second device to use the wireless transmission medium based on the timing data.

Abstract: Systems, methods, and devices for a ball grid array with non-linear conductive routing are described herein. Such a ball grid array may include a plurality of solder balls that are electrically coupled by a non-linear conductive routing. The non-linear conductive routing may include a plurality of routing sections where each of the plurality of routing sections is disposed at an angle to adjacent routing sections.

Abstract: One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, a receiver has a receiver front end configured to receive time domain data in natural order, a fast Fourier transform module configured to generate frequency domain data in digit reversed order based on the time domain data, a demodulator configured to generate first demodulated data in digit reversed order based on the frequency domain data, and a de-interleaver configured to perform a reordering permutation on the first demodulated data to generate second demodulated data in natural order.

Abstract: A method can include, by operation of a wireless device, determining at least one set of wireless channel candidates from available wireless channels of at least one wireless standard; determining a network information value accessible to devices of a wireless network; generating a selection value with an arithmetic-logic operation on the network information value; selecting a plurality of wireless channels from the at least one set of wireless channel candidates with the selection value to determine a discovery wireless channel set; and transmitting or receiving on all channels of the discovery wireless channel set in a wireless network discovery operation for the wireless network. Corresponding devices and systems are also disclosed.

Abstract: A secondary-side-controller for a QR flyback converter and method for operating the same are provided. Generally, the secondary-side-controller includes a driver configured to control a power-switch (PS) on a primary side of converter to turn on the PS when a sinusoidal input voltage to the converter is at one of a plurality of valleys, an analog-to-digital-converter (ADC) to read the input voltage, output voltage, and load current, and generate digital signals based thereon. A valley-controller coupled to the driver, ADC, a look-up-table and a pulse width modulator (PWM) receives the signals from the ADC and using the look-up-table determines at which valley of the plurality of valleys to couple a PWM signal from the PWM to the driver. The valley-controller is operable for each switching cycle of the PS to increment, decrement or leave unchanged the valley at which the PWM signal is coupled from the PWM to the driver.

Abstract: A secondary side controller for a flyback converter can include a synchronous rectifier (SR) gate driver pin coupled to a gate of an SR transistor on a secondary side of the flyback converter. An error amplifier is coupled to an output of a voltage bus of the flyback converter, the error amplifier to generate an error signal indicative of a voltage of the output of the voltage bus. Control logic is coupled to the error amplifier and to the SR transistor, the control logic to: detect when the voltage is at least a threshold percentage higher than a sink voltage required by a sink device coupled to the output of the voltage bus; detect assertion of a skip mode signal; and cause the SR transistor to be driven during a skip mode such as to partially discharge an output capacitor coupled to the output of the voltage bus.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a method of operating a Universal Serial Bus Power Delivery (USB-PD) power converter is provided. The method includes generating a pulse width modulated (PWM) signal for controlling the power converter. An output current signal for the power converter is determined. The output current signal corresponds to an output current across an external sense resistor coupled in an output path of the USB-PD power converter. A fault condition is identified based on the PWM signal and the output current signal. Operation of the power converter is disabled responsive to identifying the fault condition.

Abstract: Controlling power factor correction (PFC) in a flyback converter is described. In one embodiment, an apparatus includes a flyback converter configured to operate with a fixed switching frequency. The flyback converter includes a signal transformer, a primary side including a primary-side controller coupled to the signal transformer, and a secondary side including a secondary-side controller coupled to the signal transformer. The secondary-side controller is configured at least to cause a control signal to be generated based on a ramp voltage generated by a ramp voltage generator of the secondary-side controller. The control signal provides power factor correction (PFC) using the flyback converter.

Abstract: A method can include in a first phase of a sensing operation, controlling at least a first switch to energize a sensor inductance; in a second phase of the sensing operation that follows the first phase, controlling at least a second switch to couple the sensor inductance to a first modulator capacitance to induce a first fly-back current from the sensor inductance, the first fly-back current generating a first modulator voltage at the first modulator capacitance, and in response to the first modulator voltage, controlling at least a third switch to generate a balance current that flows in an opposite direction to the fly-back current at the first modulator node. The first and second phases can be repeated to generate a first modulator voltage at the first modulator capacitance. the modulator voltage can be converted into a digital value representing the sensor inductance. Related devices and systems are also disclosed.

Abstract: Front-end circuits that combine inductive and capacitive sensing are described. In one embodiment, an apparatus includes a plurality of inductive elements, an inductive measurement circuit, and a frequency divider circuit. The inductive measurement circuit is to output a first signal with a first frequency. The first signal is associated with an inductance change of one of the inductive elements. A feedback circuit can maintain the sinusoidal operation of the first signal. The frequency divider circuit can generate a second signal with a second frequency that is lower than the first frequency.

Abstract: An AC-DC converter and method of operating the same is provided to sense negative voltage (NSN) on a synchronous rectifier (SR_DRAIN) on a secondary-side of the converter. The SR_DRAIN voltage is sensed and a first integration signal (volt-sec) generated based on a time and voltage for which the SR_DRAIN voltage is greater than a bus voltage (VBUS_IN) output from the secondary. When Volt-sec is greater than a reference voltage a volt-sec based NSN detect signal is generated. A second integration signal (integ_resetb) is generated based on the time for which the SR_DRAIN voltage is greater than VBUS_IN. A pulse width of integ_resetb is determined using a counter, and, when it exceeds a reference by a predetermined percentage, a counter-expiry signal is generated. The volt-sec based NSN detect signal and the counter-expiry signal are logically combined to generate a real NSN detect signal when one or both are present.

Abstract: Controlling power factor correction (PFC) in a flyback converter is described. In one embodiment, an apparatus includes a flyback converter configured to operate with a variable switching frequency. The flyback converter includes a signal transformer, a primary side including a primary-side controller coupled to the signal transformer, and a secondary side including a secondary-side controller coupled to the signal transformer. The secondary-side controller is configured at least to cause a control signal to be generated based on a set of parameters. The control signal controls power factor correction (PFC) for the flyback converter.

Abstract: Implementing active clamp flyback (ACF) converters with improved efficiency is described. In one embodiment, an apparatus includes an active clamp flyback (ACF) flyback converter. The ACF flyback converter includes a primary side including a high side (HS) switch, a low side (LS) switch and an ACF driver, and a secondary side including a secondary-side controller configured at least to obtain a set of input parameters, the set of input parameters including a set of subsystem parameters associated with a subsystem and a set of system parameters associated with an initial configuration, determine a set of output parameters based on the set of input parameters, and control operation of the ACF flyback converter based on the set of output parameters.

Abstract: A wireless power transfer system is disclosed. The system includes a wireless power transmitter including a transmitter coil and a transmitter electric field shield disposed over the transmitter coil. The transmitter electric field shield includes a first printed circuit board (PCB) and a second PCB. Each of the first and second PCBs includes a number of apertures. The apertures of the first PCB do not overlap with the apertures of the second PCB. The system further includes a wireless power receiver including a receiver coil and a receiver electric field shield disposed over or underneath the receiver coil. The receiver electric field shield includes a PCB having a first layer and a second layer connected to one another. The first layer of the PCB mates with the receiver coil and the second layer of the PCB mates with an interface surface of the wireless power receiver.

Abstract: A method can include, by operation of a wireless device, monitoring at least a first advertising channel for an advertising packet; in response to advertising data in the advertising packet, synchronizing transmission and reception of packets to an advertising link that includes sub-intervals within a repeating interval on a second advertising channel. During a download sub-interval of the sub-intervals, and update packet can be received that includes new parameter data. During an upload sub-interval of the sub-intervals, transmitting an update response packet indicating the new parameter data has been received. Wireless operations of the wireless device can be configured according to the new parameter data. Communications can continue with the same advertising link while operating according to the new parameter data. Corresponding devices and systems are also disclosed.

Abstract: Systems, methods, and devices enhance data throughput in wireless devices. Methods may include determining, using a processing device comprising processing elements, a plurality of wireless parameters representing wireless data features on a wireless communications channel, and determining, using the processing device, a plurality of interference parameters based, at least in part, on the plurality of wireless parameters, the plurality of interference parameters identifying interference events on the wireless communications channel. The methods may also include generating one or more data transmission pattern modifications based, at least in part, on the plurality of interference parameters.