Abstract: A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

Abstract: A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.

Abstract: Some embodiments provide a method for optimizing a mask layout generated from a design layout of an integrated circuit (IC). The method generates, based on a first mask layout, a simulated wafer image having predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC. The method identifies a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC. The first and second IC components are related components in the IC. Based on the cross-sectional overlap, the method modifies the first mask layout to generate a modified second mask layout for the first layer.

Abstract: Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing IC components of the layer, including a first component that has a relationship with a second component on a second layer of the design layout. The method identifies, in the simulated wafer image, (i) a first set of regions of a first shape of the first component that overlap with a second shape of the second component and (ii) a second set of regions of the first shape that do not overlap with the second shape. To improve overlap between the first shape's first set of regions and the second shape, the method modifies the initial mask layout to produce a modified mask layout.

Abstract: Some embodiments provide a method for modifying a mask layout for producing masks used to manufacture an IC. The method identifies a first set of mask images corresponding to a first layer and a second set of mask images corresponding to a second layer. The method formulates a problem that expresses correlation between desired shapes of IC components and predicted as-manufactured shapes of the IC components. The IC components include components on the first layer and vias on the second layer, each via connecting a first-layer component to a component on another layer. The method solves the problem by iteratively exploring modifications to both the first and second sets of mask images to identify modified sets of mask images that result in predicted as-manufactured shapes for the components on the first layer and the vias on the second layer that sufficiently correlate to the desired shapes of the IC components.

Abstract: Some embodiments provide a method for optimizing a mask layout for producing masks for manufacturing an integrated circuit (IC) by defining multiple layers of components on a substrate. The method generates, based on a first mask layout, a simulated wafer image including representations of IC components that are predicted to be manufactured for a first layer of the IC based on a received mask layout for the first layer. The method compares the simulated wafer image to a target wafer image including optimal representations of the IC components for the first layer. The comparison uses data regarding locations of components in at least one additional layer that interact with components in the first layer. Based on the comparison, the method modifies the first mask layout to generate a modified second mask layout for the first layer.

Abstract: A method of some embodiments receives an initial first physical design of a circuit. The method uses a machine-trained network to generate a second physical design that is a prediction of how the first physical design will look at a subsequent manufacturing stage. The method then uses the second physical design to modify the first physical design. Examples of such modifications include modifying a set of one or more routes in the first physical design and/or modifying a set of placement locations of a set of one or more sub-circuits or circuit components defined in the first physical design.

Abstract: Some embodiments provide a method for optimizing a mask layout for producing masks that are used for manufacturing an integrated circuit (IC) comprising multiple layers of components. The method receives a mask layout including a set of mask images corresponding to a first layer of components of the IC that is adjacent to at least a second layer of components. The method generates a first wafer image including representations of IC components that are predicted to be manufactured for the first layer based on the received set of mask images corresponding to the first layer. Based on a positional relationship between at least one predicted IC component in the first wafer image and at least one predicted IC component in a second wafer image for the second layer, the method modifies at least one mask image in the set of mask images for the first layer.

Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose is calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.

Abstract: A system may include a device configured to receive a plurality of patterns, each pattern in the plurality of patterns comprising a plurality of edges; a device configured to determine a neighborhood open area density for the plurality of patterns; and a device configured to determine a geometric loading effect correction (gLEC). The gLEC comprises a calculated offset from an edge in the plurality of edges, where the calculated offset is determined using the neighborhood open area density, and the determining the gLEC is performed offline. A system may also include a device configured to adjust the plurality of edges using the gLEC to counteract a loading effect, where the loading effect is a difference in an amount of etching that occurs based on the neighborhood open area density, forming an adjusted plurality of edges.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments provide a method for optimizing a mask layout generated from a design layout of an IC. Based on an initial mask layout for a first layer, the method generates a simulated wafer image including shapes representing components of the first layer, including a first component that overlaps with a second component on a second layer. The method identifies a more critical first region and a less critical second region of a first shape of the first component that both overlap with a second shape of the second component. The more critical first region is more important to ensuring overlap of the first shape with the second shape. To improve overlap between the first and second shapes, the method uses different costs for the more critical first region and the less critical second region to modify the initial mask layout to produce a modified mask layout.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.

Abstract: Methods and systems involve a plurality of patterns, each pattern in the plurality of patterns comprising a plurality of edges. Methods and systems also involve determining a neighborhood open area density for the plurality of patterns; determining a geometric loading effect correction, wherein the geometric loading effect correction comprises a calculated offset from an edge of a pattern in the plurality of patterns, and wherein the calculated offset is determined using the neighborhood open area density; and adjusting the edge of the pattern in the plurality of patterns using the geometric loading effect correction.