Patents Assigned to DALSA Semiconductor Inc.
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Patent number: 8975193Abstract: A microfabricated device is fabricated by depositing a first metal layer on a substrate to provide a first electrode of an electrostatic actuator, depositing a first structural polymer layer over the first metal layer, depositing a second metal layer over said first structural polymer layer to form a second electrode of the electrostatic actuator, depositing an insulating layer over said first structural polymer layer, planarizing the insulating layer, etching the first structural polymer layer through the insulating layer and the second metal layer to undercut the second metal layer, providing additional pre-formed structural polymer layers, at least one of which has been previously patterned, and finally bonding the additional structural layers in the form of a stack over the planarized second insulating layer to one or more microfluidic channels. The technique can also be used to make cross over channels in devices without electrostatic actuators, in which case the metal layers can be omitted.Type: GrantFiled: August 2, 2011Date of Patent: March 10, 2015Assignee: Teledyne DALSA Semiconductor, Inc.Inventors: Robert Johnstone, Stephane Martel
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Publication number: 20130032210Abstract: An integrated microfluidic device has at least at least one active element controlled by pneumatic signals, and at least one electrostatic actuator integrated in the device for generating the pneumatic signals within the device from an external supply of pressure or vacuum. In one embodiment the pressure supply may be generated internally on chip using an integrated pump.Type: ApplicationFiled: August 2, 2011Publication date: February 7, 2013Applicant: TELEDYNE DALSA SEMICONDUCTOR, INC.Inventors: Robert Johnstone, Stephane Martel
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Publication number: 20130034467Abstract: A microfabricated device is fabricated by depositing a first metal layer on a substrate to provide a first electrode of an electrostatic actuator, depositing a first structural polymer layer over the first metal layer, depositing a second metal layer over said first structural polymer layer to form a second electrode of the electrostatic actuator, depositing an insulating layer over said first structural polymer layer, planarizing the insulating layer, etching the first structural polymer layer through the insulating layer and the second metal layer to undercut the second metal layer, providing additional pre-formed structural polymer layers, at least one of which has been previously patterned, and finally bonding the additional structural layers in the form of a stack over the planarized second insulating layer to one or more microfluidic channels. The technique can also be used to make cross over channels in devices without electrostatic actuators, in which case the metal layers can be omitted.Type: ApplicationFiled: August 2, 2011Publication date: February 7, 2013Applicant: TELEDYNE DALSA SEMICONDUCTOR, INC.Inventors: Robert Johnstone, Stephane Martel
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Publication number: 20130032235Abstract: An integrated microfluidic check valve has a first chamber having inlet and outlet ports and divided by a barrier the said inlet and outlet ports into first and second subchambers. A membrane forms a wall of the first chamber and co-operates with the barrier to selectively permit and prevent fluid flow between the inlet and outlet ports. A second chamber adjoining the first chamber and has a wall formed by the membrane. A microfluidic channel establishes fluid communication between the second chamber and the first subchamber. The membrane deflects to permit fluid flow around the barrier when the pressure in the first subchamber is lower than the pressure in the second subchamber. Two such valves can be combined into a peristaltic pump.Type: ApplicationFiled: August 2, 2011Publication date: February 7, 2013Applicant: TELEDYNE DALSA SEMICONDUCTOR, INC.Inventors: Robert Johnstone, Stephane Martel
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Patent number: 8071486Abstract: A method of removing residues from an integrated device, in particular residues resulting from processing in HF vapor, is disclosed wherein the fabricated device is exposed to dry water vapor for a period of time sufficient to dissolve the residues in the dry water vapor.Type: GrantFiled: July 17, 2006Date of Patent: December 6, 2011Assignee: Teledyne Dalsa Semiconductor Inc.Inventors: Vincent Fortin, Jean Ouellet
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Patent number: 7927904Abstract: A MEMS device is manufactured by first forming a self-aligned monolayer (SAM) on a carrier wafer. Next, a first polymer layer is formed on the self-aligned monolayer. The first polymer layer is patterned form a microchannel cover, which is then bonded to a patterned second polymer layer on a device wafer to form microchannels. The carrier wafer is then released from the first polymer layer.Type: GrantFiled: January 4, 2010Date of Patent: April 19, 2011Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Stephane Martel
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Patent number: 7807550Abstract: A wafer level package for a MEMS device is made by bonding a MEMS wafer and a lid wafer together to form a hermetically sealed cavity. One or more vias filled with conductive or semiconductive material is etched one of the wafers to form one or more rods extending through the wafer. The rods provide electrical connection to components within the hermetically sealed cavity.Type: GrantFiled: June 14, 2006Date of Patent: October 5, 2010Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Mamur Chowdhury
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Patent number: 7799376Abstract: A structural film, typically of silicon, in MEMS or NEMS devices is fabricated by depositing the film in the presence of a gas other than nitrogen, and preferably argon as the carrier gas.Type: GrantFiled: July 27, 2007Date of Patent: September 21, 2010Assignee: DALSA Semiconductor Inc.Inventors: Vincent Fortin, Luc Ouellet
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Patent number: 7799656Abstract: A method is disclosed for making a MEMS device wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer allowing the transfer of a layer from a Carrier Wafer to a Device Wafer.Type: GrantFiled: March 11, 2008Date of Patent: September 21, 2010Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Patrick Wright
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Publication number: 20100173436Abstract: A MEMS device is manufactured by first forming a self-aligned monolayer (SAM) on a carrier wafer. Next, a first polymer layer is formed on the self-aligned monolayer. The first polymer layer is patterned form a microchannel cover, which is then bonded to a patterned second polymer layer on a device wafer to form microchannels. The carrier wafer is then released from the first polymer layer.Type: ApplicationFiled: January 4, 2010Publication date: July 8, 2010Applicant: DALSA SEMICONDUCTOR INC.Inventors: Luc Ouellet, Stephane Martel
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Patent number: 7682860Abstract: A method of making a MEMS device is disclosed wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer to permit the transfer of a layer from a carrier substrate to a receiving substrate.Type: GrantFiled: March 16, 2007Date of Patent: March 23, 2010Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Veronique Giard, Sylvie Archambault, Paul Ignatiuk
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Patent number: 7614253Abstract: A method of making optical quality films is described. A silica film is deposited on a wafer by PECVD (Plasma Enhanced Chemical Vapor Deposition). The deposited film is then subjected to a first heat treatment to reduce optical absorption, wafer warp, and compressive stress. A second film is deposited. This step is then followed by a second heat treatment to reduce optical absorption, wafer warp and tensile stress. The two heat treatments have similar temperature profiles.Type: GrantFiled: November 17, 2006Date of Patent: November 10, 2009Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Jonathan Lachance
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Publication number: 20090242512Abstract: In a method of performing an anisotropic etch on a substrate in an inductively coupled plasma etch chamber, at least three cycles of a procedure consisting essentially of the four following steps are performed: a. depositing a protective polymer on a patterned substrate; b. performing a first low pressure etch to partially remove the deposited protective polymer at a pressure less than 40 mTorr; c. performing a high pressure etch at a pressure between between 40 mT and 1000 mT to form a portion of a trench in the substrate; and d. performing a second low pressure etch at a pressure less than 40 MTorr to reduce surface roughness. This method permits the fabrication of deep trenches with reduced surface roughness.Type: ApplicationFiled: March 24, 2009Publication date: October 1, 2009Applicant: DALSA SEMICONDUCTOR INC.Inventor: Richard Beaudry
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Patent number: 7579622Abstract: A method of making an etched structure in the fabrication of a MEMS device involves depositing a bulk layer, typically of polysilicon, prone to surface roughness. At least one layer of photo-insensitive spin-on planarizing material, such as silicate-based spin-on glass, is formed on the bulk layer to reduce surface roughness. This is patterned with a photoresist layer. A deep etch is then performed through the photoresist layer into the bulk layer. This technique results in much more precise etch structures.Type: GrantFiled: February 11, 2005Date of Patent: August 25, 2009Assignee: DALSA Semiconductor Inc.Inventor: Luc Ouellet
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Publication number: 20090029533Abstract: A structural film, typically of silicon, in MEMS or NEMS devices is fabricated by depositing the film in the presence of a gas other than nitrogen, and preferably argon as the carrier gas.Type: ApplicationFiled: July 27, 2007Publication date: January 29, 2009Applicant: DALSA SEMICONDUCTOR INC.Inventors: Vincent Fortin, Luc Ouellet
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Publication number: 20080299695Abstract: A method is disclosed for making a MEMS device wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer allowing the transfer of a layer from a Carrier Wafer to a Device Wafer.Type: ApplicationFiled: March 11, 2008Publication date: December 4, 2008Applicant: DALSA SEMICONDUCTOR INC.Inventors: Luc Ouellet, Patrick Wright
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Patent number: 7459329Abstract: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100Mpa.Type: GrantFiled: October 21, 2005Date of Patent: December 2, 2008Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Robert Antaki
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Patent number: 7439093Abstract: A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch through a mask to create a cavity under the mask, which mask is left behind as a suspended membrane above the cavity; and performing a subsequent anisotropic etch that etches anisotropically the pattern of the mask in the bottom of the cavity.Type: GrantFiled: September 16, 2005Date of Patent: October 21, 2008Assignee: DALSA Semiconductor Inc.Inventor: Richard Beaudry
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Patent number: 7365016Abstract: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.Type: GrantFiled: December 22, 2005Date of Patent: April 29, 2008Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Ghislain Migneault, Jun Li
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Patent number: 7341905Abstract: A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of sixteen specific mask steps that permit a variety of bipolar/CMOS/DMOS devices to be fabricated. The mask steps include (1) forming at least one N-well in the p-type material, (2) forming an active region, forming a p-type field region, (4) forming a gate oxide, (5) carrying out a p-type implantation, (6) forming polysilicon gate regions, (7) forming a p-base region, (8) forming a N-extended region, (9) forming a p-top region, 10) carrying out an N+ implant, (11) carrying out a P+ implant, (12) forming contacts, (13) depositing a metal layer, (14) forming vias, (15) depositing a metal layer therethrough, and (16) forming a passivation layer. Up to any three of mask steps (4), (7), (8), and (9) may be omitted depending on the type of integrated circuit.Type: GrantFiled: December 27, 2004Date of Patent: March 11, 2008Assignee: DALSA Semiconductor Inc.Inventors: Stephane Martel, Yan Riopel, Sebastien Michel, Luc Ouellet