Patents Assigned to DALSA Semiconductor Inc.
-
Patent number: 7291513Abstract: A method is disclosed for making a wafer-level package for a plurality of MEMS devices. The method involves preparing a MEMS wafer and a lid wafer, each having respective bonding structures. The lid and MEMS wafers are then bonded together through the bonding structures. The wafers are substantially free of alkali metals and/or chlorine. IN a preferred embodiment, each wafer has a seed layer, a structural underlayer and an anti-oxidation layer. A solder layer, normally formed on the lid wafer, bonds the two wafers together.Type: GrantFiled: December 7, 2004Date of Patent: November 6, 2007Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Karine Turcotte
-
Publication number: 20070231943Abstract: A method of making a MEMS device is disclosed wherein anhydrous HF exposed silicon nitride is used as a temporary adhesion layer to permit the transfer of a layer from a carrier substrate to a receiving substrate.Type: ApplicationFiled: March 16, 2007Publication date: October 4, 2007Applicant: DALSA SEMICONDUCTOR INC.Inventors: Luc Ouellet, Veronique Giard, Sylvie Archambault, Paul Ignatiuk
-
Publication number: 20070130996Abstract: A method of making optical quality films is described. A silica film is deposited on a wafer by PECVD (Plasma Enhanced Chemical Vapor Deposition). The deposited film is then subjected to a first heat treatment to reduce optical absorption, wafer warp, and compressive stress. A second film is deposited. This step is then followed by a second heat treatment to reduce optical absorption, wafer warp and tensile stress. The two heat treatments have similar temperature profiles.Type: ApplicationFiled: November 17, 2006Publication date: June 14, 2007Applicant: DALSA SEMICONDUCTOR INC.Inventors: Luc Ouellet, Jonathan Lachance
-
Publication number: 20070134927Abstract: A method of removing residues from an integrated device, in particular residues resulting from processing in HF vapor, is disclosed wherein the fabricated device is exposed to dry water vapor for a period of time sufficient to dissolve the residues in the dry water vapor.Type: ApplicationFiled: July 17, 2006Publication date: June 14, 2007Applicant: DALSA SEMICONDUCTOR INC.Inventors: Vincent Fortin, Jean Ouellet
-
Publication number: 20070065967Abstract: A method of making an etch structure in a substrate involves the steps of providing a mask on a substrate with a pattern that leaves at least one opening leaving the substrate in direct contact with the ambient, performing an isotropic or quasi-isotropic etch through a mask to create a cavity under the mask, which mask is left behind as a suspended membrane above the cavity; and performing a subsequent anisotropic etch that etches anisotropically the pattern of the mask in the bottom of the cavity.Type: ApplicationFiled: September 16, 2005Publication date: March 22, 2007Applicant: DALSA Semiconductor Inc.Inventor: Richard Beaudry
-
Publication number: 20070015341Abstract: A wafer level package for a MEMS device is made by bonding a MEMS wafer and a lid wafer together to form a hermetically sealed cavity. One or more vias filled with conductive or semiconductive material is etched one of the wafers to form one or more rods extending through the wafer. The rods provide electrical connection to components within the hermetically sealed cavity.Type: ApplicationFiled: June 14, 2006Publication date: January 18, 2007Applicant: DALSA SEMICONDUCTOR INC.Inventors: Luc Ouellet, Mamur Chowdhury
-
Patent number: 7160752Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.Type: GrantFiled: October 5, 2005Date of Patent: January 9, 2007Assignee: Dalsa Semiconductor Inc.Inventors: Luc Ouellet, Robert Antaki
-
Patent number: 7144750Abstract: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100 Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100 Mpa.Type: GrantFiled: June 12, 2003Date of Patent: December 5, 2006Assignee: Dalsa Semiconductor Inc.Inventors: Luc Ouellet, Robert Antaki
-
Patent number: 7138293Abstract: A method is disclosed for fabricating a integrated device, such as a MEMS device. A first wafer is provided on an exposed surface with a layer of gold, gold alloy or gold compound. A second wafer is provided on its exposed surface with under-layer of gold, gold alloy or gold compound; and an over- of bismuth, bismuth alloy, a compound of bismuth, cadmium, cadmium alloy, a compound of cadmium compound, tin, tin alloy, or a compound of tin. The wafers are then brought into contact and bonded at their surfaces through the deposited layers.Type: GrantFiled: December 6, 2002Date of Patent: November 21, 2006Assignee: Dalsa Semiconductor Inc.Inventors: Luc Ouellet, Jules J Poisson
-
Publication number: 20060211163Abstract: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.Type: ApplicationFiled: December 22, 2005Publication date: September 21, 2006Applicant: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Ghislain Migneault, Jun Li
-
Patent number: 7101754Abstract: A method of making a film with a high dielectric constant uses a spin-on sol-gel process to deposit the film on a substrate, the film having a composition (SiO2)x(TiO2)1?x, where 0.50<x<0.75. The resulting film is annealed in an oxygen-containing atmosphere at a temperature lying in the range of 500° C. to 700° C.Type: GrantFiled: June 10, 2004Date of Patent: September 5, 2006Assignee: DALSA Semiconductor Inc.Inventors: El Khakani My Ali, Sarkar Dilip K., Luc Ouellet, Daniel Brassard
-
Publication number: 20060166403Abstract: A micro-electro-mechanical (MEM) device and an electronic device are fabricated on a common substrate by fabricating the electronic device comprising a plurality of electronic components on the common substrate, depositing a thermally stable interconnect layer on the electronic device, encapsulating the interconnected electronic device with a protective layer, forming a sacrificial layer over the protective layer, opening holes in the sacrificial layer and the protective layer to allow the connection of the MEM device to the electronic device, fabricating the MEM device by depositing and patterning at least one layer of amorphous silicon, and removing at least a portion of the sacrificial layer. In this way, the MEM device can be fabricated after the electronic device on the same substrate.Type: ApplicationFiled: October 5, 2005Publication date: July 27, 2006Applicant: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Robert Antaki
-
Publication number: 20060110895Abstract: A method of fabricating a silicon-based microstructure is disclosed, which involves depositing electrically conductive amorphous silicon doped with first and second dopants to produce a structure having a residual mechanical stress of less than +/=100 Mpa. The dopants can either be deposited in successive layers to produce a laminated structure with a residual mechanical stress of less than +/=100 Mpa or simultaneously to produce a laminated structure having a mechanical stress of less than +/=100 Mpa.Type: ApplicationFiled: October 21, 2005Publication date: May 25, 2006Applicant: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Robert Antaki
-
Patent number: 7037745Abstract: In the manufacture of a MEMS device having a semiconductor-on-insulator substrate with a first portion closed by a lid to provide a hermetically sealed region and an second portion external to said hermetically sealed region, a method of providing electrical connections to said hermetically sealed region comprising forming at least one continuous deep trench in said semiconductor and extending down to said insulator, said at least one deep trench surrounding and isolating at least one block of semiconductor within said substrate, and said at least one block of semiconductor extending form within said first region to said second region; depositing an insulating layer in said trenches and over the surface of said substrate; depositing a metal ring around said first region; sealing said lid to said metal ring; and attaching a contact to said at least one block of semiconductor in said second region to provide one or more electrical connections through said at least one block of semiconductor to one or more compoType: GrantFiled: May 6, 2004Date of Patent: May 2, 2006Assignee: DALSA Semiconductor Inc.Inventor: Luc Ouellet
-
Publication number: 20050277304Abstract: A method of making a film with a high dielectric constant uses a spin-on sol-gel process to deposit the film on a substrate, the film having a composition (SiO2)x(TiO2)1-x, where 0.50<x<0.75. The resulting film is annealed in an oxygen-containing atmosphere at a temperature lying in the range of 500° C. to 700° C.Type: ApplicationFiled: June 10, 2004Publication date: December 15, 2005Applicant: DALSA Semiconductor Inc.Inventors: El My Ali, Sarkar Dilip K., Luc Ouellet, Daniel Brassard
-
Patent number: 6937806Abstract: A method of making a photonic device having at least two layers formed over a substrate, preferably by plasma enhanced chemical vapor deposition, involves depositing a thin spin-on glass (SOG) interlayer between at least one adjacent pair of layers to improve the roughness characteristics.Type: GrantFiled: March 21, 2002Date of Patent: August 30, 2005Assignee: Dalsa Semiconductor Inc.Inventor: Luc Ouellet
-
Publication number: 20050145962Abstract: A method of making an etched structure in the fabrication of a MEMS device involves depositing a bulk layer, typically of polysilicon, prone to surface roughness. At least one layer of photo-insensitive spin-on planarizing material, such as silicate-based spin-on glass, is formed on the bulk layer to reduce surface roughness. This is patterned with a photoresist layer. A deep etch is then performed through the photoresist layer into the bulk layer. This technique results in much more precise etch structures.Type: ApplicationFiled: February 11, 2005Publication date: July 7, 2005Applicant: DALSA Semiconductor Inc.Inventor: Luc Ouellet
-
Publication number: 20050142685Abstract: A method is disclosed for making a wafer-level package for a plurality of MEMS devices. The method involves preparing a MEMS wafer and a lid wafer, each having respective bonding structures. The lid and MEMS wafers are then bonded together through the bonding structures. The wafers are substantially free of alkali metals and/or chlorine. IN a preferred embodiment, each wafer has a seed layer, a structural underlayer and an anti-oxidation layer. A solder layer, normally formed on the lid wafer, bonds the two wafers together.Type: ApplicationFiled: December 7, 2004Publication date: June 30, 2005Applicant: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Karine Turcotte
-
Publication number: 20050136599Abstract: A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material.Type: ApplicationFiled: December 27, 2004Publication date: June 23, 2005Applicant: DALSA Semiconductor Inc.Inventors: Stephane Martel, Yan Riopel, Sebastien Michel, Luc Ouellet
-
Patent number: 6902656Abstract: A cavity forming formed in an encapsulation structure under a vacuum in a vacuum chamber is sealed with a capping layer. A stiff protective layer under tensile stress is deposited on the capping layer prior to venting the vacuum chamber to atmospheric pressure. The capping layer is preferably aluminum or an aluminum alloy, and the protective layer is preferably ?-TiN having a suitable high Young's modulus.Type: GrantFiled: May 24, 2002Date of Patent: June 7, 2005Assignee: DALSA Semiconductor Inc.Inventors: Luc Ouellet, Robert Antaki, Yves Tremblay