Patents Assigned to DALSA Semiconductor Inc.
  • Patent number: 6896821
    Abstract: A method of making an etched structure in the fabrication of a MEMS device involves depositing a bulk layer, typically of polysilicon, prone to surface roughness. At least one layer of photo-insensitive spin-on planarizing material, such as silicate-based spin-on glass, is formed on the bulk layer to reduce surface roughness. This is patterned with a photoresist layer. A deep etch is then performed through the photoresist layer into the bulk layer. This technique results in much more precise etch structures.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 24, 2005
    Assignee: DALSA Semiconductor Inc.
    Inventor: Luc Louellet
  • Patent number: 6887514
    Abstract: To deposit optical quality films by PECVD (Plasma Enhanced Chemical Vapor Deposition), a six-dimensional space wherein five dimensions thereof correspond to five respective independent variables of which a set of four independent variables relate to the flow-rate of respective gases, a fifth independent variable relates to total pressure, and a six dimension relates to observed FTIR characteristics is first created. Then an optical film is deposited while maintaining three of the set of four independent variables substantially constant as well as the fifth independent variable, and varying a fourth of the set of four independent variables to obtain desired characteristics in the sixth dimension.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: May 3, 2005
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Luc Ouellet, Jonathan Lachance, Manuel Grondin, Stephane Blain
  • Patent number: 6849491
    Abstract: A process for making a integrated circuits of different typed is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence is chosen from a predefined common set of mask steps according to the particular type of integrated circuit to be fabricated. In this way, various types of integrated circuit can be fabricated in a most efficient manner.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: February 1, 2005
    Assignee: DALSA Semiconductor Inc.
    Inventors: Stephane Martel, Yan Riopel, Sebastien Michel, Luc Ouellet
  • Patent number: 6833282
    Abstract: In order to make a charge couple device including an interconnect layer to contact active areas, a first layer of a first titanium nitride layer on the active areas, and then a series of alternating titanium and titanium nitride layers are deposited to form a composite sandwich structure. This structure is less prone flaking while able to withstand high temperature treatment during fabrication of backside illuminated sensors to improve quantum efficiency and reduce dark current.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: December 21, 2004
    Assignee: DALSA Semiconductor Inc.
    Inventors: Robert Groulx, Raymond Frost, Yves Tremblay
  • Patent number: 6770213
    Abstract: A method is disclosed for evaluating an anisotropic etch in a microstructure. First a film is formed on a substrate. Next a series of holes of progressively different area and having specific geometric shapes are formed through the film. An anisotropic etch is carried out in the microstructure through the holes by relying on different etch rates in different crystal planes under known and reproducible conditions. Finally, the microstructure is inspected through the holes after the anisotropic etch to compare results from holes of different area. The method is useful in the determination of etch depth.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: August 3, 2004
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Robert Antaki, Riopel Yan
  • Patent number: 6749893
    Abstract: A method for making an integrated photonic device involves depositing buffer, core and cladding layers on the front side of a wafer. A thick tensile stress layer is deposited on the back side of the wafer just prior to performing a high temperature thermal treatment above 600° C. on the cladding layer to prevent the cracking of the layers as a result of the thermal treatment.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: June 15, 2004
    Assignee: DALSA Semiconductor Inc.
    Inventors: Luc Ouellet, Jonathan Lachance, Sylvie Archambault
  • Patent number: 6724967
    Abstract: A method is disclosed for making a device having one or more deposited layers and subject to a post deposition high temperature anneal. Opposing films having similar mechanical properties are deposited on the front and back faces of a wafer, which is subsequently subjected a high temperature anneal. The opposing films tend to cancel out stress-induced warping of the wafer during the subsequent anneal.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: April 20, 2004
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Luc Ouellet, Annie Dallaire
  • Patent number: 6716476
    Abstract: A method is disclosed for depositing an optical quality silica film on a wafer by PECVD. The flows rates for a raw material gas, an oxidation gas, a carrier gas, and a dopant gas are first set at predetermined levels. The total deposition pressure is set at a predetermined level. The deposited film is then subjected to a post deposition heat treatment at a temperature selected to optimize the mechanical properties without affecting the optical properties. Finally, the observed FTIR characteristics of the deposited film are monitored to produce a film having the desired optical and mechanical properties. This technique permits the production of high quality optical films with reduced stress.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: April 6, 2004
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Luc Ouellet, Jonathan Lachance
  • Patent number: 6686214
    Abstract: In order to align a mask to a specific crystal plane in a wafer, a first mask having at least one alignment structure is deposited on the wafer surface. The alignment structure is coarsely aligned with the specific crystal plane and has an array of components that are offset relative to each other by known angles defining the degree of precision with which said mask can be finely aligned with said crystal plane. Next, an anisotropic etch is performed through the first mask to etch the alignment structure into the wafer surface. The components of the alignment structure produce different etch patterns in the wafer surface according to their relative orientation to the specific crystal plane. Finally, a second mask is formed on the wafer surface having a reference structure thereon. The reference structure on the second mask is aligned relative to an etch pattern identified as being finely aligned with the specific crystal plane.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: February 3, 2004
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Robert Antaki, Riopel Yan, Annie Vachon
  • Patent number: 6656528
    Abstract: A method of making highly reflective mirrors on a wafer in the manufacture of photonic devices involves preheating a wafer to remove adsorbed volatile contaminants at a temperature between about 300 and 600° C. The wafer surface is etched at a temperature between about 300 and 600° C. to remove absorbed and chemically absorbed contaminants in the presence of a plasma to prevent poisoning. The wafer surface is thoroughly cooled so as to as reduce the surface mobility of the impinging atoms during the subsequent metallic deposition. A deposition is then carried out on the cooled wafer of a gettering layer for gettering hydrogen, oxygen and nitrogen. A metallic reflective layer is then deposited in a deposition chamber, and finally the wafer is removed from the deposition chamber to prevent excessive bulk oxidation.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: December 2, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Luc Ouellet, Yves Tremblay
  • Patent number: 6635509
    Abstract: A competitive, simple, single-substrate wafer-level packaging technique capable of creating a vacuum-sealed protective cavity around moving or other particular components of a MEMS is described. The technique uses common semiconductor materials, processing steps and equipment to provide a stable vacuum environment of, for example less than 1 Pa, in a sealed cavity. The environment protects components of the MEMS against micro-contamination from particles and slurry of a waver dicing process and against fluctuations of atmospheric condition to ensure long term reliability.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: October 21, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventor: Luc Ouellet
  • Patent number: 6602791
    Abstract: In a method of fabricating a microstructure for microfluidics applications, a first layer of etchable material is formed on a suitable substrate. A mechanically stable support layer is formed over the etchable material. A mask is applied over the support to expose at least one opening in the mask. An anistropic etch is then performed through the opening to create a bore extending through the support layer to said layer of etchable material. After performing an isotropic etch through the bore to form a microchannel in the etchable material extending under the support layer, a further layer is deposited over the support layer until overhanging portions meet and thereby close the microchannel formed under the opening.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: August 5, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Luc Ouellet, Heather Tyler
  • Patent number: 6598610
    Abstract: Thick dielectric films are deposited on a substrate by building up a plurality of layers by PECVD (Plasma Enhanced Chemical Vapor Deposition) in a reactor, each layer having a thickness less than the final thickness of the film to be deposited. The reactor is cleaned between the deposition of each layer. In this way, it is possible to form high quality, optical films.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: July 29, 2003
    Assignee: DALSA Semiconductor Inc.
    Inventors: Stephane Blain, Sylvie Harrison
  • Patent number: 6573133
    Abstract: A sidewall spacer is formed in a CMOS device by depositing a layer of silicon nitride on a wafer and anisotropically etching away the silicon nitride layer with a chorine-based plasma etchant.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: June 3, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Marc Roy, Manon Daigle, Bruno Lessard, Ginette Couture
  • Patent number: 6555441
    Abstract: A method is disclosed for aligning structures on first and second opposite sides of a wafer. First one or more transparent islands are formed on the first side of the wafer at an alignment location. The transparent islands have an exposed front side and a rear side embedded in the wafer. At least one alignment mark is formed on the front side of the transparent island. An anisotropic etch is performed through the second side of said the to form an opening substantially reaching the back side of the transparent island. A precise alignment is then carried out on the alignment mark through the opening and the transparent island. In this way a very precise alignment can be carried out on the back side of the wafer for manufacturing MEMS structures.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: April 29, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventor: Luc Ouellet
  • Patent number: 6537623
    Abstract: An improved high temperature chemical treatment of deposited silica films wherein they are subjected to a reactive ambient comprising hydrogen and oxygen atoms. This method results in better elimination of residual undesirable oscillators so as to provide improved optical quality silica waveguides with reduced optical absorption.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: March 25, 2003
    Assignee: Dalsa Semiconductor Inc.
    Inventors: Luc Ouellet, Manuel Grondin