Abstract: In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.

Abstract: The processor of the present invention can execute any of a plurality of dialects of "S-Language" instructions. S-Languages are of a higher order than typical machine languages but of a lower order than the user's own high order language. They can be tailored for compatibility with user high order languages. Each instruction of a particular S-Language is interpreted by a sequence of microinstructions. In the processor of the present invention, dispatching to the microinstruction sequencer is controlled jointly by the instruction bit pattern and the current contents of a dialect register. Each procedure to be executed carries with it information from which the appropriate contents of the dialect register may be determined. Thus, the processor of the present invention can always operate as an effective optimum processor for executing the procedure regardless of the source language chosen for writing that procedure.

Abstract: Apparatus whereby a single component of electrical apparatus may be disconnected from one of a group of components and connected to another of the group in response to a break code. The apparatus includes a break code detector which generates a select signal in response to a break code and switching means which respond to the select signal by disconnecting the single component from one of the group of components and connecting it to another of the group. The apparatus may also include a display responsive to break codes for showing which component of the group is currently connected to the single component. In embodiments in apparatus having break codes consisting of a sequence of one state longer than that found in any other digital code, the break code detector includes apparatus for measuring intervals between occurrences of the state other than that making up the break code and thereby detecting break codes.

Abstract: Apparatus and method for generating monitor synchronization signals in a terminal capable of operating at either a 31.5 Khz or 15.75 Khz horizontal video scan rate is disclosed. A first set of counters count incremental locations along each horizontal scan line. The outputs of these counters are provided to a memory which provides a blanking signal and three synchronization signals. The memory also provides a clocking input to a second set of counters which count horizontal scan lines. These second counters are preloaded to values which depend on the scan mode selected, the frame being displayed, the refresh rate and whether a vertical video or vertical blanking operation is underway. A second memory receives the outputs of the second counter set, the frame being displayed and the refresh rate signal and provides selection inputs used to choose the signals to be provided as the composite blanking and composite monitor synchronization signals.

Abstract: A digital data bus system for connecting a controller and a disk drive. Data on the disk is stored in track sectors containing a header and data. The controller includes a high-speed processor which performs a header compare operation comparing the values received from a header with the expected contents of the header and operations which determine when all of the data in a track sector has been transferred. The digital data bus system includes a bus for transferring data between the controller and the disk drive and a header-data mode bus for providing a header mode signal and a data mode signal from the controller to the disk drive. During an operation transferring data between the controller and the disk, the disk drive responds to the header mode signal by transferring a header to the controller.

Abstract: An integrated digital network (IDN) includes a matrix and user signal ports for exchanging voice, data, IDN control, and building control digital signals between the matrix and user equipment, the digital signals comprising single samples of each signal type from each user port in each IDN sample time interval, the IDN further including a transmission system for concentrating user port digital signal samples of each sample time interval, by common signal type, into multiple bit channel signals for exchange between the user ports and matrix signal ports of the matrix switch, the matrix switch interconnecting each channel signal from one or more user ports to one or more other user ports.

Abstract: Apparatus in a disk drive connected by separate buses to two controllers for suspending the effect of a reserve instruction received from one controller when the other controller has already reserved the disk drive until the other controller releases the disk drive. The apparatus corresponding to each controller consists of suspended reserve logic and a register for retaining state indicating whether the controller has reserved the bus and state indicating whether the reserve operation has been suspended for the controller. The suspended reserve logic for a given controller receives inputs from the controller's bus, from the state stored in its register, and from the state in the suspended reserve apparatus for the other controller indicating whether that controller has reserved the disk drive. Outputs from the suspended reserve logic go to its register.

Abstract: Encoding-decoding apparatus having an internal data path for diagnostic use. The apparatus includes control apparatus for providing signals controlling operation of the encoding-decoding apparatus, an input device connected to a source of data to be encoded and a source of data to be decoded, an output device connected to a destination for the encoded data and a destination for the decoded data, and apparatus connected between the input device and the output and device for performing the encoding and decoding. A data path responsive to the control signals receives encoded data from the output device and provides it to the input device.

Abstract: A data processing system having a host processor and an attached processor is disclosed. Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing system memory but the host processor controls and performs all input and output operations for both processors. System memory is shared by the processors, therefore, only one processor is active on the bus system at any given time. Apparatus is disclosed for holding the host processor and starting the attached processor upon a command from the host and apparatus is disclosed for holding the attached processor and starting the host in the event of interrupt conditions, attempted access by the attached processor to protected areas of memory, or execution of an "out" instruction by the attached processor. Memory mapping apparatus which is under host control, but provides mapping for both the host and attached processors is shown.

Abstract: A digital computer system having a memory system organized into objects for storing data and a processor for processing data in response to instructions. An object identifier is associated with each object. The memory system responds to logical addresses for data which specify the object containing the data and the offset of the data in the object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions. Each instruction contains an operation code which belongs to one of several sets of operation codes. All instructions in a single procedure belong to a single operation code set, and associated with each procedure is an operation code set identifier specifying the operation code set to which the instructions in the procedure belongs.

Abstract: A method of forming CMOS transistors with self-aligned field regions comprising the steps of providing on a silicon substrate first and second spaced apart areas for said CMOS transistors followed by forming a masking member on said substrate protecting the first of said areas and exposing the second. The second area is doped with a p-type material after which the size of the unmasked area is increased to that defining a p-well region to be formed therein surrounding said second area. Once the p-well region is formed, the same mask is employed to dope the p-well region with additional p-type material after which the CMOS transistors are fabricated in said first and second spaced apart areas.

Abstract: A digital data processing system using process synchronization techniques which comprise processing await logic for suspending the execution of a program controlled by a process, virtual processor await logic for performing an await operation at the virtual processor level and for temporarily inhibiting the loading of state items for the execution of the program, virtual processor advance logic for performing an advance operation at the virtual processor level to cease the inhibition of the loading of such state items, and process advance logic for causing the processor of the system to resume execution of the suspended program which is under control of the process.

Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.

Abstract: An access control system for use in a digital computer system wherein the memory system is organized into objects, a data item is locatable by specifying an object, instructions are contained in procedures, and the operations performed by the system include a call operation for suspending an execution of a procedure and commencing another execution and a return operation for terminating an execution and resuming a suspended execution. The access control system associates each procedure with a domain, i.e., a set of objects accessible to the procedure. The access control system further includes a secure stack object which is accessible only to the access control system. When a call operation commences execution of a procedure which has a different domain, the access control system responds to the call operation by storing information required to return to the current domain in the secure stack.

Abstract: A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege.

Abstract: A pulse width modulator circuit for use with DC power converters. The circuit contains an oscillator having a nonlinear output, a first comparator for comparing the output of the oscillator with an input voltage, and a second comparator for selecting portions of the output waveform of the first comparator for supplying to the output of the modulator.