Abstract: An apparatus for incorporation in each memory-using component of a data processing system permits locking of a portion of the memory, which portion may be as small as a single location, for atomic read-modify-write operations while permitting unlimited access to the memory for read operations and access to all but the locked portion for non-atomic write operations.

Abstract: A communications node for handling circuit and packet switching and capable of expansion to include multiple switching matrices, multiple network processors and multiple packet processors is disclosed. Each switch matrix has multipile I/O ports and communications with user interfaces, network interfaces and other system components via bidirectional data links. At least one switch matrix is connected via a bidirectional data link to a packet processor and a network processor. All processors are interconnected via a computer bus. Switch matrices are connected to each other either by a backplane bus or via bidirectional data links.

Abstract: Methods and apparatus are set forth which improve the efficiency of bandwidth usage over the CCITT I.463 standard, for switching systems having a granularity of better then 64 Kbps (e.g. 8 Kbps). Furthermore, methods and apparatus are set forth which are capable of performing rate adaptation for synchronized sub-rate channels in a manner geared to package sub-rate data in fragment size envelopes (or integer multiples thereof), where the width of a fragment is matched (ideally equal) to the granularity of the system's switch. This improves the efficiency of the rate adaptation process and maximizes the use of the system's switching and bandwidth capacity.

Abstract: Methods and apparatus are set forth which provide for the allocation of bandwidth for point-to-point, serial, bidirectional communication paths in a digital switching system. Bandwidth allocation is performed at both ends of a path (e.g. T1 line, IML, etc.) and may take place in either direction. Furthermore, according to the preferred embodiment of the invention, the Bandwidth Allocation Facility (BAF) at each end of a given path allocates bandwidth in integer multiples of maximum switching system granularity. The BAF also supports the implementation of user requests for any one of a plurality of allocation and boundry rules. To minimize the probability of contention and out of band signalling between the BAF pair associated with a given path, a front-to-back search mechanism is assigned for one BAF of the pair, while the other BAF utilizes a back-to-front search mechanism.

Abstract: A data processing system which includes a memory and a processor comprising at least two execution units. The system further includes a microcode control unit for storing sequences of microinstructions and an execution microinstruction stack containing at least one stack frame containing the machine state of a first execution unit when the execution of a microinstruction has been interrupted. A memory microinstruction stack is provided to store a plurality of stack frames, stack frames being transferrable between the execution microinstruction stack and the memory microinstructiion stack. The microcode control unit contains sequences of monitor microinstructions and has associated with it a minotor microinstruction stack for storing the machine state of the first execution unit when the execution of a monitor microinstruction has been interrupted.

Abstract: A data processing system which includes a host processor and an input/output (I/O) controller unit for controlling communication with I/O devices. The I/O controller unit responds to a plurality of I/O commands from the host processor each of which is associated with one of a plurality of control block lists each containing one or more control commands. The I/O controller unit can access and store control commands from each of the plurality of control block lists and execute the stored commands from such lists in a selected order for providing the most effective execution thereof.

Abstract: A memory for use in a digital data system stores n-bit words, and provides for accessing any group of n contiguous bits, regardless of whether aligned on an n-bit boundary. Barrel shifters facilitate rotating the retrieved bits so as to align them as convenient.

Abstract: An initialization or synchronization method in which at least a predetermined number of synchronization messages are sent out over a two-way communication line. The receipt of a synchronization message is awaited before terminating the transmission of synchronization message. After the transmission of synchronization messages has been terminated the receipt of a non-synchronization message will complete the synchronization process. However, certain conditions may cause synchronization to be restarted such as a predetermined number of consecutive error messages, failure to receive any message in a predetermined number of clock signals, receiving more than a predetermined number of synchronization signals, or a reset command.

Abstract: A computing system is disclosed which uses a system busy signal on its system bus to help control access to said bus. One or more requesters can generate a request signal when the system busy signal is not asserted. System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. A freeze signal is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. The freeze signal may be generated by a memory control unit, a memory module or a requester.

Abstract: A data processing system which includes a host processor and an input/output (I/O) controller unit for controlling communication with I/O devices. The controller processor receives I/O commands from the host processor, accesses and stores control block lists of control commands associated with such I/O commands, and executes the control commands from such control block lists. The controller unit stores controller information concerning the operational capability of the controller unit and the host processor is capable of accessing such controller information and in turn can modify such operational capability if desired.

Abstract: A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.

Abstract: A microcomputer is disclosed having a LIFO memory employed as a stack, and a shift register employed as a stack pointer for controlling access to the stack. There is no need to decode the contents of a stack pointer. Thus, high speed of operation is possible.

Abstract: A data processing system in which the interface for connecting a host controller to a burst multiplexor channel comprises two sections one to handle the transfer of data and the other to handle the transfer of command and status information. The interface also includes logic to monitor the division of any transfer into bursts and logic to arbitrate for the two sections for any given burst.

Abstract: A method is disclosed which enhances the ability of digital computer system to manage displays, especially in an environment where a single physical display supports a plurality of logical displays (windows). Machine-language instructions are provided which, in conjunction with user-supplied form descriptors describing each of the windows, enable management and generation of display image data to be performed directly by the processing hardware of the digital computer system, eliminating any need for intervening interpretive software. Data computed from form descriptors may be encached, enhancing the speed of consecutive operations on windows. Graceful creation is enhanced by permitting processing control to escape to software fault handlers.

Abstract: An improved content addressable memory cell which employs a structure which utilizes a single transistor to discharge the hit line, and is driven by a self-blocking driver which glitchlessly changes state without the use of virtual nodes. Also disclosed is an alternative content addressable memory cell which can be written into in two distinct fashions, one of which permits the content of the cell to be changed without requiring the entire data word with which the cell is associated to be rewritten.

Abstract: A communications network comprising nodes interconnected by communication lines employs a method of allocating data rates to fragments of line bandwidth which facilitates efficient allocation of available line bandwidth. Each node maintains, for each communication line connected to it, a bit map means having a bit position associated with each fragment available in the line for keeping track of which fragments are available and which are in use. Identification of available bandwidth fragments in the line is then accomplished by finding appropriate bit values in the bit map means; fragments allocated are marked in the bit map means. A node thus need not allocate fragments contiguously, and available bandwidth is equally allocable by either of the two nodes interconnected by a particular line.

Abstract: An optimizer-code generator for use in a data base system. The optimizer-code generator employs a component called a scan analyzer for performing implementation-dependent analysis and providing implementation-dependent query code. The optimizer-code generator receives a query in logical tree form. It first optimizes the logical tree. In so doing, it provides information from the logical tree to the scan analyzer, which specifies what methods are available for accessing information required for the query and what each of the available methods costs. The optimizer-code generator uses the cost information in its optimization of the logical tree and specifies the access methods to be used in the logical tree. The code generator then uses the logical tree to generate query code. In so doing, it provides the specifications of the access methods to the scan analyzer, which returns query code for the access method.

Abstract: An apparatus provides a sequence detected signal indicating that a synchronization sequence occurring at regular intervals in a stream of data has occurred or should have occurred. The apparatus includes logic for detecting the synchronization sequence, logic responsive to the detection logic for producing the sequence detected signal when the detection logic detects the sequence, and logic for producing the sequence detected signal at a fixed time after the synchronization sequence should have occurred. If the synchronization sequence did occur, the apparatus thus produces two sequence detected signals; however, the device receiving the sequence detected signal responds to the first sequence detected signal and ignores the second. If the synchronization sequence did not occur, the device receiving the sequence detected signal responds to the sequence detected signal produced by the logic responsive to the timing apparatus.

Abstract: A universal addressing system for use in a digital data processing system including a universal memory for storing data including instructions and at least one local system having access to the universal memory. The universal memory is organized into objects, and each item of data is associated with an object. Each object is specified by a unique identifier, and data is addressed by means of a logical address which specifies the UID of the object containing the data and the offset of the data in the object. A processor in the local system responds to instructions by providing memory operation specifiers to the universal memory. Each memory operation specifier specifies a memory operation and a logical address. The offset in the logical address may specify any bit in the object. The memory operation specifier also specifies a length in bits.

Abstract: A phase comparator for use in a phase-locked loop, responsive to CLOCK and DATA signals, for producing UP and DOWN commands exhibiting a difference in duration proportional to the phase difference between the CLOCK and DATA signals, for controlling the charge pump of the loop, can be used with half-clock times as fast as one gate delay and one flip-flop delay, rendering it useful for high-speed operation.