Abstract: A method for providing on-line replacement of a module which is at a specified position in an array of modules connected to a common control processor so that all other modules in the array can continue operating during the replacement operation. When the module is removed an indication is provided to the control processor showing that removal has occurred and identifying the position thereof. When the replacement has occurred an indication thereof is provided to the control processor, the replacement module is tested, and the state of the replacement module is updated to place it in the same state it would have been in if it had not been replaced.

Abstract: A method for handling data in a plurality of data storage disks having user data sectors and corresponding parity sectors, the method being used when the disks are being operated in a degraded mode wherein data in sectors of an inoperative user data disk are reconstructed from data in the corresponding sectors of the other user data disks and the corresponding parity entry. The reconstructed user data in a user data sector of the inoperative disk is written into the corresponding parity sector in place of the parity entry therein, before any new data is written into the corresponding sector of an operative disk. Information identifying the inoperative disk is written into a specified identification region of the parity disk to indicate that such operation has occurred. The new data is then written into the corresponding sector of the operative disk.

Abstract: A communication protocol available to any type module on the computer bus. Application programs are treated as clients or servers. A serveport is created in the server module. A client issues a connect request to the server identifying the serveport. The server assigns a N-slot TID capability to identify, describe and protect a storage location for receiving a start buffer from the client and sends the N-slot TID to the client to establish a connection. The start buffer includes a TID list which permits the client and server to reliably communicate back and forth. Once a connection has been established, data can be moved between the server and the client. High-level instructions and commands are sent as data through these connections. After the communication has been completed, the connection can be disconnected by the client or broken by the server.

Abstract: A distributed computer system having a plurality of digital computer systems interconnected by a bus. Each digital computer system runs one or more programs. When it receives a command directed to a system device or a program, it determines whether it can fulfill the command. If not, it determines which one of the other digital computer systems can fulfill the command based upon retaining information stored locally and forwards the command to the other digital computer system.

Abstract: A disk array subsystem for use in a data processing system. In one embodiment, the disk array subsystem comprises a generally rectangular chassis having a top wall, a bottom wall, a pair of side walls, an open front end and an open rear end. Disposed within the chassis are three power supplies, a pair of controller boards, a backplane, and a set of twenty disk drive modules. A mounting structure comprising four first disk drive module guide plates and a pair of second disk drive module guides is fixedly mounted within the chassis for removably mounting the disk drive modules in the chassis through the open front end and for placing the disk drive modules in approximate alignment with the backplane for electrical connection therewith. Each first guide plate is shaped to include five parallel slotted channels, and each second disk drive module guide plate is shaped to include ten parallel grooves.

Abstract: An improved memory system for use in a data processing system which memory system has two memory banks and corresponding error correction circuitry associated with each. Data words of a block thereof are stored in the memory banks in an interleaved fashion wherein alternating words are stored in one bank and intervening alternating words are stored in the other bank. During a write operation the memory is controlled so that the first data word of a block stored in a memory bank uses a late write technique and all subsequent data words thereof use an early write technique. During a read operation, pairs of data words are read and checked for errors simultaneously and are then supplied in a pipelined manner.

Abstract: A method and system for handling a branch instruction which requires branching from a current instruction of a first instruction sequence to the first instruction of a second instruction sequence. The branch instruction is fetched and the next instruction of the first sequence is fetched while the branch instruction is displacement formatted. The first instruction of the second sequence is fetched while such next instruction is displacement formatted and the branch instruction is executed. The second instruction of the second sequence is fetched while the first instruction is displacement formatted, but the next instruction of the first sequence is not executed so that an execution wait occurs. The third instruction of the second sequence is then fetched while the second instruction is displacement formatted and the first instruction is executed.

Abstract: An apparatus and method for handling data transfer between a synchronous keyboard and a host processor is disclosed. An asynchronous receiver/transmitter is employed in conjunction with logic for controlling the keyboard clock and data lines to permit the receipt of data from and the transmittal of data to the keyboard in a pseudo-synchronous manner.

Abstract: A printed circuit board assembly includes a printed circuit board having a top side, a bottom side and a hole. A heat spreader which comprises a plate made of a material having high thermal conductivity is mounted on the bottom side of the printed circuit board. The plate includes a pedestal which extends up into the hole. A high density TAB IC chip is mounted on top of the pedestal and is electrically connected to pads on the top side of the printed circuit board. A heat pipe is mounted underneath the plate of the heat spreader through a mounting pad which is fixed to the heat pipe and which is made of a material having good thermal conductivity. In operation, heat generated by the chip during use is spread out by the heat spreader and then removed by the heat pipe.

Abstract: A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.

Abstract: Methods and apparatus are set forth for quickly making switched virtual connections (SVCs) in a digital circuit switch that integrates voice and data using common switch, control and distribution equipment. SVCs provide concurrent data connection service from one station device, such as a PC, to other station devices over a single line for each station device where the line may also carry voice and terminal data service. A switch control processor remembers connection requests from station devices and acts on opportunities to utilize available bandwidth in an optimal manner. Dynamic connection reconfiguration techniques allow the system to "scavenge" bandwidth unused by voice or terminal data traffic for SVCs thereby providing the largest possible data rate at any given time. Short signalling messages and indexed values are used in order to speed activation time for previously defined connections while resource allocation is performed by the switch control processor to further enhance system operating speed.

Abstract: Methods are set forth which provide for the allocation of bandwidth for point-to-point, serial, bidirectional communication paths in a digital switching system. Bandwidth allocation is performed at both ends of a path (e.g. T1 line, IML, etc.) and may take place in either direction. Furthermore, according to the preferred embodiment of the invention, the Bandwidth Allocation Facility (BAF) at each end of a given path allocates bandwidth in integer multiples of maximum switching system granularity. The BAF also supports the implementation of user requests for any one of a plurality of allocation and boundary rules. To minimize the probability of contention and out of band signalling between the BAF pair associated with a given path, a front-to-back search mechanism is assigned for one BAF of the pair, while the other BAF utilizes a back-to-front search mechanism.

Abstract: An integrated office controller (IOC) network includes, in combination, a plurality of station devices each capable of transmitting and receiving multiplexed bearer and signal channel information; user port interface means for carrying said multiplexed information between a station device and a station multiplex/demultiplex device (SMX); a plurality of SMXs, each associated with and coupled to a predefined cluster of said station devices, via said user port interface means, for concentrating the multiplexed information froms said interface means into channel signals, central equipment module (CEM) means, including a call processor, a non-blocking switch matrix and clock means, for switching channel signals through said switch matrix under the control of said cell processor and clock means; transmission system means, capable of interfacing SMXs and trunk cards to said CEM, where said transmission system means includes modular line interface module (LIM) means for interfacing a plurality of SMXs and the CEM, an

Abstract: A communication link interface having an assembly register which is loaded in response to a transmitter's clock rate and unloaded in response to a receiver's clock connected to the interface. The assembly register holds a series of data words received from the communication link. Logic gates or flip flops are provided to insure a time delay between loading the assembly register and unloading it.

Abstract: Methods and apparatus are set forth which improved the sub-rate channel carrying capacity and the efficiency of bandwidth usage, over the CCITT I.463 standard, for switching systems having a switching "granularity", defined as the smallest channel size that can be switched through the system, of better then 64 Kbps (e.g. a switching system that can switch 8 Kbps fragments). These methods and apparatus are capable of performing rate adaptation for multiple synchronized subrate channels in accordance with a predefined multiplexing protocol. The protocol calls for "time interleaved" multiplexed rate adaptation to be performed, i.e., multiple sub-rate channel data is packaged into fragment size envelopes (or integer multiples thereof). The width of a fragment is also matched (ideally equal) to the granularity of the system's switch.

Abstract: Methods and apparatus are set forth that perform Format Conversion between bit streams which embed sub-rate circuit data according to different protocols. The invention (1) locates and extracts the sub-rate circuit data embedded, in an input serial bit stream, in accordance with a first predefined protocol (2) aligns the data in a buffer, and (3) creates an output bit stream in which the extracted circuit data is reformatted and inserted in accordance with a second predefined protocol. A programmable bit map driven format conversion module operates the data aligned in the aforementioned buffer. The conversion process is bidirectional and, in one embodiment of the invention, facilitates conversion between a single stage time division multiplexed data format and a two stage time division multiplexed format (e.g. X.50 and I.463) by utilizing the aforesaid bit map driven format conversion technique.

Abstract: A system for use in a floating point computation unit for providing a sign/magniture subtraction operation, which system uses propagate/generate logic responsive to the subtraction operands to produce intermediate and final propagate and generate outputs. First carry computation logic is responsive to the final propagate and generate outputs and to a carry-in bit to produce final carry outputs and a carry-out bit. The latter outputs are used to produce a first subtraction result. Second carry computation logic responds to the intermediate propagate and generate outputs to produce second final carry outputs. The latter outputs and selected intermediate propagate outputs are used to produce a second subtraction result. The carry-out bit then selects one of the two subtraction results as the final subtraction result.