Abstract: A method and apparatus for optimizing cooling system performance using full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for optimizing the cooling of an electronic system incorporating at least one semiconductor chip includes receiving full-chip temperature data for the semiconductor chip(s) and configuring the cooling system for dissipating heat from the electronic system in accordance with the full-chip temperature data.

Abstract: Methods, systems, and devices for designing and/or analyzing of integrated circuits are disclosed.

Abstract: An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order of a plurality of tasks in the hierarchical collection of stages. Parameters customize the plurality of tasks. The relational constraints and parameters are hierarchically defined, such that higher order definitions in the hierarchical collection of stages override lower level definitions of the relational constraints and parameterized knobs.

Abstract: A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physical layers includes defining at least one thermal layer within the plurality of physical layers, where the thermal layer(s) represents a variance in thermal conductivity relative to a remainder of the semiconductor chip design, and computing a thermal conductivity of the thermal layer(s). As the thermal layer(s) represents variances in thermal conductivity over the semiconductor chip design, the thermal layer(s) does not necessarily correspond one-to-one to the physical layers of the semiconductor chip design. Thus, the thermal conductivities within the semiconductor chip design can be computed from the thermal layers.

Abstract: Electronic Design Automation tools are used to aid in the design and verification of integrated circuits. As part of the verification process, circuit designs are analyzed with respect to their timing performance. Timing analysis is susceptible to variation in circuit components due to fabrication process variation. Process variation is introduced as worst-case conditions or statistical probabilities. More accurate process variation is modeled by for timing sensitivity with Parametric Elmore Delay. Parametric Elmore Delay introduces effects on circuit components as parameters in the conventional Elmore Delay definition to model fabrication process variation in the timing analysis. Delay variance demonstrates sensitivities to process and design factors. Parametric timing analysis is used to anticipate fabrication yield and identify potential improvements in the design or fabrication process.

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating performance, scalars for transient performance are determined for strongly couple components. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: An automated design process and chip description system is disclosed. The automated design process and chip description system compensates for the loss in design information that occurs when the design is represented in traditional functional descriptions. The automated design process includes the steps of processing a design definition according to a functional description and generating a modified design output such that communication between design process steps is seamless. The chip description system comprises a storage element and a functional element, wherein a first design object couples to a second design object such that the coupling uses at least one functional element to access one or more storage elements usable by the chip description system.

Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Abstract: A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When estimating performance, the invention partitions an integrated circuit into strongly coupled components. The technique accurately estimates of the performance (e.g., transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

Abstract: A computer-implemented method computes the steady-state and control voltage of a voltage controlled oscillator, given a known frequency or a known period of oscillation of the voltage controlled oscillator. Differential algebraic equations representative of the voltage controlled oscillator are generated, where the differential algebraic equations includes a known period or frequency of oscillation and an unknown control voltage of the voltage controlled oscillator. The differential algebraic equations are modified using a finite difference method, a shooting method, or a harmonic balance method, to obtain a set of matrix equations corresponding to the differential algebraic equations. A solution to the matrix equations is obtained using a Krylov subspace method, using a preconditioner for the Krylov subspace method that is derived from a Jacobian matrix corresponding to the matrix equations, where the solution includes the control voltage of the voltage controlled oscillator in steady state.

Abstract: A method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A relative floorplanning constraint is extracted from the floorplan design. The floorplan of the integrated circuit is updated in response to the relative floorplanning constraint. Another method for designing integrated circuits includes receiving a floorplan design associated with an integrated circuit. A set of relative floorplanning constraint is received from the floorplan design. A relative floorplanning constraint is pushed down from the set of relative floorplanning constraints into a partition associated with the floorplan of the integrated circuit. The floorplan is updated in response to the set of relative floorplanning constraints.

Abstract: An electronic design automation method of placing circuit components of an integrated circuit (“IC”) is provided. A synthesized circuit netlist including one or more soft macros is received and a rough global placement of this netlist is performed. A shaper function is determined. The shaper function evaluates a cost of a current placement of the one or more soft macros based on one or more constraints and one or more penalty functions which are associated with the one or more constraints. Moreover, the current placement is optimized to produce a subsequent placement of the one or more soft macros by minimizing the cost. Furthermore, where the netlist includes one or more hard macros, a legalization requirement is applied to the one or more hard macros.

Abstract: An integrated circuit and a method for using metal fill geometries to reduce the voltage drop in power meshes. Metal fill geometries are connected to the power mesh using vias or wires at multiple locations. Metal fill geometries are connected to other floating metal fill geometries using vias or wires at multiple locations. The circuit design introduces maximum redundancy between metal fill geometries and power mesh geometries, but partial redundancy between metal fill geometries and metal fill geometries. In particular, the redundancy in connectivity between metal fill geometries and metal fill geometries is kept minimal to reduce the number of geometries introduced. The high redundancy between metal fill geometries and power mesh geometries and the partial redundancy among metal fill geometries result in a smaller IR-drop by reducing the effective resistance on a power mesh.

Abstract: To perform functional verification of a digital design that includes one or more datapaths, a formal verification system includes a datapath abstraction tool. The datapath abstraction tool detects a datapath in a circuit design and performs an appropriate abstraction of the datapath. The tool may also deduce datapath elements from identified ones as well as link the abstractions of particular datapath elements. The abstraction tool then passes the circuit design with the abstraction to the verification software to simplifying the formal verification process.

Abstract: Aspects of the present invention include a methodology for the general timing-driven iterative refinement-based approach, a timing-driven optimization (TDO) method that optimizes the circuit depth after the area oriented logic optimization, and a layout-driven synthesis flow that integrates performance-driven technology mapping and clustering with TDO to account for the effect of mapping and clustering during the timing optimization procedure of TDO. The delay reduction process recursively reduces the delay of critical fanins of a selected. Furthermore, in one embodiment, the fanins of the selected node are sorted according to their slack values.

Abstract: A system and a method are disclosed for performing a timing or signal propagation delay analysis on a circuit. The disclosure includes representing a drive logic stage as a representative linear circuit driven by a current source. The current source is represented as a function of a current at a constant value, a start time, a tail-start time, and a time constant of an equivalent capacitive circuit. Once the current source model is constructed, a logic stage can be analyzed for timing or signal propagation delay using conventional linear circuit analysis techniques. The disclosure also is applicable to resistance capacitance (“RC”) interconnect circuits using a current source model in which an RC load is represented as an effective capacitance and the current source for use in a linear analysis is constructed using an iterative approach.

Abstract: A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

Abstract: A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing performance analysis of a semiconductor chip design includes receiving at least one input calculated in accordance with an actual (e.g., purposefully calculated rather than assumed or estimated) temperature of a semiconductor device and/or an interconnects in the semiconductor ship design. This input is then used to assess at least one temperature-dependent performance parameter of the semiconductor chip design.

Abstract: A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design comprises receiving at least one input relating to a semiconductor chip design to be analyzed. The input is then processed to produce a three-dimensional thermal model of the semiconductor chip design. In another embodiment, thermal analysis of the semiconductor chip design is performed by calculating power dissipated by transistors and interconnects included in the semiconductor chip design and distributing power dissipated by the interconnects.