Abstract: A circuit for decoding additional information in a composite signal, the circuit having a filter device for separating a signal range in the composite signal, which includes the additional information in coded form. An adaptive decoding device is controlled by a signal quality parameter which is determined in an additional circuit from the respective reception state of the composite signal.
Abstract: A transmission system and a transmitter (T) for such a system are disclosed for transmitting a digital signal (sr), encoded in symbols (Si), from the transmitter (T) to a receiver (R) at an arbitrary frequency position by quadrature modulation. In the transmitter, one of the two quadrature components (ki, kq) is delayed before the quadrature modulation by a given time interval (td).
Abstract: A method identifying components is disclosed. Measured values of a randomly produced property of the component are recorded. The measured values are biuniquely assigned to the component by means of a characteristic parameter and the measured values accessibly storing the measured values, or a unique code assigned thereto. Further, the characteristic parameter are accessibly stored.
Abstract: A process for separating electronic devices connected with one another in a body, the process including thinning the side of the body remote from the electronic devices, separating the electronic devices, and testing electrical parameters of the electronic devices after the thinning of the body. The handling of the body is improved by applying to the side of the body containing the electronic devices, prior to the thinning process, an electrically nonconductive auxiliary layer in which respective contact openings are formed above the electronic devices to expose the contact(s) of the respective electronic device.
Abstract: A logical block is disclosed for decoding a data sequence encoded by a convolutional code, in which a given number of states are to be evaluated. These given states are assigned the given number of state memories which store an associated path and an accumulated distance value. The given number of state memories are associated with parallel processing blocks which each have, as the smallest group to be processed in parallel, two state memories to be read from first and second parallel processing blocks, and two state memories to be written into third and fourth parallel processing blocks. Optimum memory organization permits simple parallel processing and reduction in circuit complexity.
Abstract: A process is disclosed for making contact to differently doped regions in a semiconductor device which are disposed in a silicon substrate in different depths, a first region with a first dopant concentration and/or conductivity type and the smaller depth being disposed in a second region with a second dopant concentration and/or conductivity type and the greater depth, and a first metal layer being deposited on the first region. A second metal layer is deposited on a portion of the first metal layer, and the structure is subjected to a heat treatment in which contact is made to the first region through the first metal layer and to the second region through the first metal layer and the second metal layer.
Abstract: Transmission system with a transmitter (T), a receiver (R), and a filter combination (FI1, FI2; FQ1, FQ2) for transmitting a digital signal (sr), encoded in symbols (Si), from the transmitter (T) to the receiver (R) at any frequency position by quadrature modulation, wherein one of the two quadrature signal components (ki, kq) in the transmitter is delayed before the quadrature modulation by a time interval td, particularly by td=Tsymb/4. (FIG.
Abstract: A semiconductor structure for creating resistor networks, particularly ladder networks, has resistive sections made of semiconductor material and metal contact areas. A continuous semiconducting resistor strip is provided as a primary arm. Along this continuous primary arm, metal contact areas which contact the resistor strip at the side are provided in accordance with the desired resistor ratio and in order to form corresponding series resistors. In a ladder network, shunt arms have one end connected directly to the long side of the primary arm via the semiconductor material. At the other end of each of the shunt arms, a respective metal contact area is provided.
Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.
Abstract: A virtual reality system permanently connected with a device to be worn by a user is disclosed which has an optical position-sensing facility that contains at least one radiation source defining a fixed reference point in space and an optical receiving system permanently connected with the device. The optical receiving system includes three radiation detectors, whose optical axes are parallel to each other. The first radiation detector has a reception pattern which shows a rising/falling sensitivity characteristic in a first angular range. The second radiation detector has a reception pattern which shows a rising/falling sensitivity characteristic in a second angular range. The third radiation detector has a reception pattern which shows a slowly varying sensitivity characteristic within at least the first and second angular ranges.
Abstract: A monolithic integrated sensor circuit is disclosed comprising a sensor system for generating an electronic sensor signal; a supply unit for the sensor system; an amplifying stage for amplifying the sensor signal; a plurality of inverting devices in the signal path of the amplifying stage which reverse the polarity of the sensor signal at equal time intervals, the time intervals and inversion of the sensor signal being controlled by a clock signal source; and an averaging combiner stage whose input receives an amplified sensor signal and whose output has a reference polarity which is controlled by means of the inverting devices in such a way as to be always the same regardless of the switching state in the signal path. The monolithic integrated sensor circuit of the present invention minimizes the offset error.
Abstract: A method for separating elements associated within a body includes creating a separation region within the body, between the elements, leaving a region of the body which is to be thinned. The method then requires depositing a delay layer on the body, with an opening around the separation region. The delay layer has a predetermined removal rate relative to the removal rate of the body. Lastly, the method requires removing a predetermined amount of the delay layer, the separation region, and the region of the body to be thinned. Preferably, the removing is accomplished by etching, such as plasma etching, and the etch rate of the delay layer is lower than the etch rate for the separation region. In a preferred method, the predetermined removal rate and the positions of the openings in the delay layer are selected so that upon after etching, the elements remaining have a predetermined locus dependent thickness.
Abstract: A circuit is disclosed for modifying a first signal and a second signal from a signal source providing at least two signals. The circuit including devices for forming signal components from the first and second signals. The signal components are then combined into a modified first signal and a modified second signal by means of a first combining device and a second combining device, respectively.
Abstract: A video signal clamping circuit for adapting the DC level of a composite video signal to the processing range of a digital video signal processing device, includes an isolating capacitor in the analog video signal path and a controlled current source which is connected to a floating isolating-capacitor terminal and charges or discharges the isolating capacitor solely by means of a positive or negative clamping current, with the value and sign of the clamping pulses being digitally controlled by a comparator circuit which compares predetermined reference values of the composite video signal with mode-dependent comparison values.
January 30, 1997
Date of Patent:
August 25, 1998
Deutsche ITT Industries GmbH
Herbert Elmis, Heinrich Koehne, Herbert Alrutz, Hermann Zibold
Abstract: A method of separating electronic devices contained in a carrier which are provided at the surface of the carrier and are covered by a protective layer. Openings are provided above separation regions between adjacent electronic devices. The material of the carrier is removed in the separation regions starting from the openings, and the electronic devices are, at least during the material-removing process, confined in the carrier by respective regions with a material removal property different from that of the carrier.
Abstract: A multiplier for real or complex numbers is split at each data input into two equally large digit ranges to determine partial products in separate subfields. Within a rectangular partial-product field, the subfields are rearranged according to the real or complex arithmetic operation to be performed, the rearrangement being effected by assigning basic weights to the individual subfields. By means of an adding arrangement, the partial products of the individuals subfields are added in a positionally correct manner to form the digits of a real or complex output number.
Abstract: Digital demodulator for a quadrature-modulated signal (sq) which transmits a combination signal by amplitude and phase modulation. A quadrature-signal source provides a digitized in-phase component (I) and a digitized quadrature component (Q) of low frequency. A resolver converts the two components (I,Q) into a magnitude signal (b) and a first phase signal (p1). A first feedback control loop and a second feedback control loop that maintains the slope (mp) of the first phase signal (p1) at the zero value and the time average (pm1) at the zero phase position, whereby a third phase signal (p3) is formed. From the resulting signals (b, p3, p3') a decoder forms at least one of the required components (R,L,P).
Abstract: A monolithic integrable mixer network for a mixer console includes a variable gain preamplifier for each sound channel, a summing amplifier whose summing gain is adjustable differently for each sound channel, and a control unit which divides the channel gain for the respective sound channel between the preamplifier and the summing amplifier according to a ratio dependent on the desired channel gain to optimize the noise performance of the mixer network.
Abstract: An iterative interpolator permits linear interpolation between a first known value and second known value, which are defined by n-coordinate values in an n-dimensional coordinate system. An intermediate value to be interpolated is defined by n-1 intermediate values. By an interval nesting process in a first coordinate direction, an approximate value is formed for the first intermediate value. A copying device transfers this interval nesting process to the required coordinate value in the other coordinate direction.
Abstract: A complementary clock system is disclosed for producing antiphase clock signals. The system includes a clock generator for producing a first clock signal (t3) and a second clock signal (t4). A first and second driver stage coupled to the clock generator for driving respective clock lines having a capacitive load that corresponds to a first load capacitance and a second load capacitance, respectively. A switchable current path coupled between the first and second clock lines which contains a gating circuit and at least one inductive element. The gating circuit being in a conducting state essentially during the switching intervals (ti) of the first and second clock signals (t3, t4).