Abstract: A shift register is disclosed in which an n-stage shift-register chain (sr) consists of 2n series-connected, like basic cells (zi) which are driven in antiphase by a first and a second shift clock (C1, C2) from a clock generator (g). The nonoverlap range of the two shift clocks is temperature- and frequency-stable, so that the shift register can be used within a wide frequency and temperature range. Frequency adaptation is accomplished simply by changing resistance values.

Abstract: The invention relates to battery-operated appliances, and to an improved battery storage compartment. The battery (47, FIG. 7) lies in a compartment in a housing (20), the housing having a front face containing controls (28, 30) and a display (26). An aperture (44) lies in the housing front face to enable battery replacement from the front, and a cover (110) covers the aperture. The cover has ports (124) through which plugs (122) pass to reach sockets (32). A circuit board (36, FIGS. 3 and 4) lies behind the rear wall (134) of the battery compartment, the circuit board having about as great a width and length as the housing.

Abstract: To further reduce the manufacturing costs of semiconductor devices, such as TO-92 transistors or thyristors, a prefabricated plastic can or housing is filled with cast resin, and the chip, together with its leads and a synthetic-resin cover, is inserted into the cast resin and the can, with portions of the leads engaging a groove in the can. The apparatus for inserting the chips, etc., into the cans includes a feed rail for the cans, a centering slide, and a swivelling gripper onto which the cans are pushed by the centering slide. When rotated, the swivelling gripper slips the cans over the chips mounted on a lead frame moving above the swivelling gripper.

Abstract: A portable electronic picture recording device includes a camera, an A/D converter for converting the analog picture signal to digital picture data, a signal processing and control circuit for compressing the digital picture data for storage and for restoring the data on playback and for processing the picture signal frames in single-picture, multi-picture, and scene shooting (sequence) modes, an electronic memory having erasable, programmable, nonvolatile memory cells, and a D/A converter for converting restored digital picture data into analog output signals. The electronic memory has EEPROM cells formed at a high packing density with VLSI technology, so that the picture recording device can have camcorder-like functions without a moving storage medium and with comparatively low power consumption.

Abstract: A method is disclosed for forming implanted wells and islands of CMOS integrated circuits with a retrograde profile, i.e., with wells and islands having a smaller penetration depth, shallower doping profile, and less lateral diffusion than in conventional CMOS circuits.

Abstract: An improved digital video signal processing circuit, for common use in the recording and playback modes of a video tape recorder, has a chrominance processing circuit for processing the chrominance signal of the input digital composite video signal through a first baseband mixer, a chrominance processor, and a second baseband mixer, and a luminance processing circuit for frequency modulating/demodulating the luminance signal, so that the processed chrominance and luminance signals can be added together to form an output digital composite video signal. The improved digital circuit automatically regulates the frequencies of the mixing signals for both mixers using line stepping signals obtained from a horizontal line sweep generator in the luminance processing circuit. The possibility of phase errors is eliminated, and quadrature errors in the chrominance signal are prevented.

Abstract: A digital control circuit with a device for generating a high-resolution tuning voltage is suitable for use in receivers for RF signals, particularly in consumer equipment. The tuning voltage can be electronically switched from one value to another at a high speed. The transient time required with conventional control loops is nearly eliminated since the low-pass filter or the digital integrator is preset to its steady-state integration value. To generate the tuning voltage, dynamic digital-to-analog convertors are provided which, despite their high resolution, require only a smoothing filter with a short response time and a short time constant.

Abstract: In a frequency modulation system, a modulating signal is split into its low-frequency and high-frequency components. The low frequency component is used to modulate a carrier signal by conventional means in a first circuit and the low- and high-frequency components are used to narrowband modulate the carrier signal in a second circuit. The outputs of the first and second circuits are combined to provide a frequency modulated signal. The modulating and carrier signals can be binary-coded signals.

Abstract: A transconductance amplifier is driven by a difference voltage which is coupled through a first input terminal to a first voltage-to-current converter and through a second input terminal to a second voltage-to-current converter of identical design. An identical third voltage-to-current converter has its input terminal connected to the tap of a resistive voltage divider which is connected between the first and second input terminals. The output signal of the transconductance amplifier can be taken from the current outputs of the first and second voltage-to-current converters. The current outputs have a difference current which is proportional to the value of the difference voltage.

Abstract: An offset-voltage-balancing operation amplifier for difference signals includes an auxiliary and a main amplifier, each having a difference input and an auto-zero input. To provide offset balancing, the auto-zero inputs are connected to the potentials of two integrated storage capacitors. The difference input of the auxiliary amplifier can be short-circuited via first and second switching means, and the two storage capacitors are connected to the output of the auxiliary amplifier via third and fourth switching means. The sensitivity of the auto-zero inputs is less than the sensitivity of the difference inputs.

Abstract: A two-phase clock generator generates a nonoverlapping two-phase clock from a unipolar input clock by utilizing gate delays in first and second signal paths. The output of each signal path is fed over a cross-coupled feedback path back to a logic gate in the respective other signal path. Each logic gate is a floating inverter having a first supply terminal connected to a supply voltage, and having a second supply terminal that is the feed point for the respective feedback signal from the output of the other signal path.

Abstract: In an electrooptical arrangement for remotely controlling an electronic apparatus with a remote control transmitter, the transmitter is formed with three sources of radiation whose radiation patterns are different from each other and can be comparatively detected relative to each other to indicate the tilting of the transmitter in different reference plane directions. A radiation detector at the receiver side detects the different radiation intensities for the signals from the three sources, and the relation between the signal intensities is evaluated to determine the tilt angles of the remote control transmitter in the reference plane directions.

Abstract: This semiconductor device has two leads (3) lying in the same axis, a prefabricated plastic can (1) which is filled with a plastic compound and has one of the leads passed through its bottom (1a), and a prefabricated die (4) attached between those sides of the inner ends (60, 70) of the leads (3) facing each other, the leads being inserted into, and having an offset within, the can.In the manufacturing method the manufacture of the leads starts with a wire (30) which unwinds from a spool (39), passes through a major part of the manufacturing stages unseparated, and is separated into the individual semiconductor devices only after the mounting of the cans (1).

Abstract: A digital deemphasis circuit for the BTSC multichannel television standard includes a square-root extractor, a digital filter having the transfer function F(z)=(b-ac)/(z+a), where a, b and c are constants that determine the frequency response of the digital filter. The digital deemphasis circuit further includes a subcircuit that transforms the output signal from the square-root extractor into three quantities w1, w2, w3 that are applied as multiplicands to three multipliers to control the operation of the deemphasis circuit.

Abstract: The test-probe manipulator for a test probe for use with semiconductor wafers utilizes three adjusting spindles (50,51,52) arranged on the same side of the manipulator. The test-probe manipulator occupies little space and is easy to operate. All three axes of translational freedom perform linear motions independent of each other. Accuracy of adjustment is improved as compared to conventional devices. Easy placement on and removal from a test platform are ensured.

Abstract: A collector contact (6) is fabricated which is attached on the side to the collector zone (1), and around which a moat (3) is produced which laterally restricts the collector zone (1). The depth of the moat (3) is so dimensioned to be at least equal to the vertical thickness of the collector zone (1). The collector contact (6) comprises a polycrystalline silicon layer which contains dopants of the same conductivity type as the collector zone (1), and covers a highly doped contacting zone (7') which has been diffused from the adjoining collector contact (6).

Abstract: A programmable logic array implemented with complementary insulated-gate field effect transistor technology and formed on a substrate employing a standard AND-OR structure and two non-overlapping clock phases uses diffused capacitors in a dummy row to model the worst case evaluation time of minterms in the AND plane, and a NOR gate, responsive to the dummy row, for enabling the OR plane to sum the minterms generated by the AND plane.

Abstract: A color television channel that includes a video channel and at least one sound channel is converted by means of a low-IF converter from the RF band directly to the baseband by analog quadrature conversion. The quadrature output signals are digitized. A correcting stage eliminates the quadrature errors and forms a corrected quadrature pair which drives a video stage and a sound conversion stage. The sound conversion stage includes at least one sound channel converter which converts the low-IF sound channel to its baseband by another (digital) quadrature conversion.

Abstract: A central processor for digital signal processing operates at a high clock rate. In the central processor, data is transferred and processed largely in parallel and simultaneously. A buffer is inserted in the data link between a data memory and an ALU by means of at least three data buses so that within one clock period, all necessary data transfers for a two-address operation of the ALU are performed by using the buffer. In particular, a unidirectional data bus and a bidirectional data bus transfer data from the buffer to the ALU, and the bidirectional data bus transfers the result of an ALU operation back to the buffer. Simultaneously with the transfers between the buffer and the ALU, a data transfer is performed between the data memory and the buffer. The data transfers and the data processing are controlled by a control unit in which a fixed program is stored segment by segment. The use of pipelining in the control unit permits a high processing speed.

Abstract: A remote control system, particularly for television sets, includes a remote control receiver and a remote control transmitter. The receiver and transmitter are switched to the menu mode by means of a menu key. At least two menu fields are associated with the remote control receiver and are displayed on the screen of the television set. The menu fields are individually selectable by means of the remote control transmitter. The selection is preferably accomplished by manually aligning the remote control transmitter with the displayed menu field to be selected.