Abstract: A memory test engine performs memory tests on an embedded memory located in a device under test (DUT) simultaneous to analog tests performed by an automatic tester. The automatic tester provides coded information to the memory test engine, which includes a description of the embedded memory within the DUT. The memory test engine operates autonomous to the automatic tester; apply addresses, data and control and comparing results of the memory test to expected values. The automatic tester and the memory test engine use the same DUT data bus; and therefore, arbitrate the use of the bus of the DUT.

Abstract: A floating gate pixel is described which is formed by forming an N well in a P type silicon substrate. A P well is formed in the N well A gate is formed over a thin gate oxide, about 25 Angstroms thickness, such that the gate is directly over part of the P well and part of the N well. A P+ contact in the P well allows connection to a reset voltage source, usually through a reset transistor, to reset the pixel. The pixel is reset by setting the potential between the P well and the substrate, which is usually held at ground potential. When the pixel is reset tunneling current through the thin gate oxide sets the voltage of the floating gate. During the charge integration cycle an input signal to the pixel, such as a light signal, changes the potential of the pixel. After the charge integration cycle the tunneling current through the gate oxide changes the potential of the floating gate by an amount related to the input signal to the pixel.

Abstract: A CMOS pixel responsive to different colors of optical radiation without the use of color filters is described. A deep N well is formed in a P type silicon substrate. An N well is then formed at the outer periphery of the deep N well to form a P well within an N well structure. Two N+ regions are formed in the P well and at least one P+ region is formed in the N well. A layer of gate oxide and a polysilicon electrode is then formed over one of the N+ regions. The PN junction between the deep N well and the P type silicon substrate is responsive to red light. The PN junction between the deep N well and the P well is responsive to red light. The PN junction between the P well and the N+ region which is not covered by polysilicon and the PN junction formed by the N well and the P+ region are responsive to green or blue light. The PN junction formed by the junction between the P well and the N+ region which is covered by polysilicon is responsive to green light.

Abstract: A new electronic imaging system is achieved. The system comprises a sensor having a first color region, a second color region, and a third color region. A prism system comprises a first prism having a first index of refraction and overlying the first color region. The first prism directs incident light of the first color to the first color region of the sensor. A second prism has a second index of refraction and overlies the second color region. The second prism directs incident light of the second color to the second color region of the sensor. A third prism has a third index of refraction and overlies the third color region. The third prism directs incident light of the third color to the third color region of the sensor.

Abstract: An active pixel sensor comprising an N well of n type silicon formed in a p type silicon substrate and a P well of p type silicon is formed in the N well. A deep N well is formed of n type silicon underneath the P well. The edges of the deep N well contact the bottom of the N well forming an overlap region which can either be not depleted of charge carriers thereby electrically connecting the N well to the deep N well or depleted of charge carriers thereby electrically isolating the N well from the deep N well. N regions formed in the P well and P regions formed in the N well are used to reset the pixel and to read the pixel after a charge integration period. An array of P wells formed within N wells can be used to form an array of active pixel sensors. In this array an overlap region is formed between each N well and the deep N well.