Abstract: A method of communication on a shared media having a plurality of devices coupled thereto, the method including: forming a first portion including information on a property of a data signal and complying with a communication protocol; forming a second portion comprising data that differs from the information on the property provided in the first portion, where the second portion is non-compliant with the communication protocol; forming a third portion comprising an error check character to verify that the data signal is error free, where the error check character is purposefully set to be an incorrect value and otherwise complying with the communication protocol; and transmitting the data signal including the first, second, and third portions on the shared media, whereby a first of the plurality of devices that complies with the communication protocol is configured to reject the data signal due to the purposefully incorrect error check character.

Abstract: A method of charging a battery having a first voltage and a second voltage. In a first phase, applying a constant current to the battery; in a second phase, applying current pulses to the battery; repeating iteratively sampling the first voltage during a current pulse to obtain a measurement of the first voltage; sampling the first voltage during a current pause to obtain a measurement of the second voltage; generating a dynamic reference voltage based on the fixed reference voltage and on a difference between the measurement of the first voltage and the second voltage. There is a comparing the measurement of the first voltage with the dynamic reference voltage. There is a stopping of the current pulses when the measurement of the first voltage is equal to the dynamic reference voltage and the measurement of the second voltage is equal to the fixed reference voltage.

Abstract: A power converter is presented. The power converter may be configured to receive an input voltage at an input node of the power converter and to generate an output voltage at an output node of the power converter. The power converter may comprise an inductor coupled between an inductor node and the output node. The power converter may comprise a flying capacitor coupled between a first capacitor node and a second capacitor node. The power converter may comprise a first switching element coupled between the input node and the first capacitor node. The power converter may comprise a second switching element coupled between the second capacitor node and the inductor node. The power converter may be configured to, during a first phase of a buck operation mode, open the second switching element such that the second capacitor node is isolated from the inductor node.

Abstract: A current monitoring circuit for use with an inductor having a magnetizing phase and a de-magnetizing phase is presented. The current monitoring circuit has a voltage controlled oscillator and a first counter. The voltage controlled oscillator generates a clock signal based on a voltage across the inductor. The first counter generates a counter value using the clock signal. The current monitoring circuit may be implemented as part of a switched mode power supply having an inductor coupled to a pair of power switches and a controller adapted to generate a control signal to control the pair of power switches based on the counter value.

Abstract: A ripple reduction circuit for use with an AC/DC power supply providing an output voltage to a load is presented. The ripple reduction circuit includes an input terminal for receiving the output voltage and a low pass filter. The low pass filter is used to filter an AC component of the output voltage to obtain a filtered DC voltage. The ripple reduction circuit generates a reference current based on the filtered DC voltage and a control voltage having an AC component in phase with the AC component of the output voltage.

Abstract: A flyback converter is provided that includes a high-side synchronous rectifier switch transistor. A secondary-side synchronous rectifier controller powered by a power supply voltage controls a cycling on and off of the high-side synchronous rectifier switch transistor. An active control of the charging of the power supply voltage uses an auxiliary capacitor that is charged from a charge source while a power switch transistor in a first switching state. When the power switch transistor is in a second switching state that is the complement of the first switching state, the active control coupes the auxiliary capacitor to a power supply capacitor that stores the power supply voltage.

Abstract: A system for providing end-to-end data protection between a transmitting end device and a receiving end device is presented. The system has a transmitting end device to calculate a first check value for a first message, which has first and second data blocks; the receiving end device; and a remapping device. The remapping device is configured to remap a data block among the first and second data blocks for generating a second message for the receiving end device. The remapping device also determines a remapping value based on the data block and the remapped data block, such that a second check value that would be calculated for the second message would be equal to the first check value, and wherein the second message comprises the other one of the first and second data blocks, the remapped data block, and the remapping value.

Abstract: A power converter configured to generate an output voltage at an output node of the power converter based on an input voltage received at an input node of the power converter is presented. In particular, the power converter may comprise a first switching element coupled between the input node and a first intermediate node. The converter also has an inductive element coupled between a second intermediate node and the output node, a second switching element with one port being coupled to the second intermediate node and a third switching element and a fourth switching element coupled in series between the output node and a reference node. The converter also has a flying capacitive element coupled between the first intermediate node and a third intermediate node between the third and fourth switching elements and a fifth switching element coupled between the first and second intermediate nodes.

Abstract: A key word detection apparatus and a method for low-power voice-activated devices are presented. A first signal processing module operates with a first transducer to receive an incoming signal and generates a first sample. A second signal processing module operates with a second transducer which receives an incoming signal and generates a second sample. In summary, a signal processing system, in particular a key word detection system, has a first low power module that wakes up a second higher power module. The second module uses signals from the first module in order to improve accuracy of key word detection or other signal processing tasks.

Abstract: A digital signal processing system for multiplying a digital value and a digital signal. The digital signal processing system receives the digital value in an encoded format, and multiplies the digital value with the digital signal. The digital value in the encoded format has an offset, which is encoded as a floating point. The disclosure provides a digital processing system that can carry out a multiplication operation with a smaller area, less complexity and/or reduced power usage compared with known multipliers.

Abstract: The present document relates to power converters. A power converter has a first stage coupled between an input of the power converter and an intermediate node, and a second stage coupled between the intermediate node and an output of the power converter. The first stage has a capacitive voltage divider with a first flying capacitor, and the second stage has a second flying capacitor and an inductor. On the one hand, the power converter establishes, in a magnetizing state, a magnetizing current path in the second stage from the intermediate node via the inductor to the output of the power converter. On the other hand, the power converter establishes, in a capacitive state, a parallel current path in the second stage from the intermediate node via the second flying capacitor to the output of the power converter.

Abstract: A method of authenticating a first device at a second device for two wirelessly communicating devices, the method comprising: determining the distance between the two devices based on a property of a received communication; at each device, determining at least one shared physical layer property of the communication channel between the two devices; and authenticating the first device based on the determined distance between the two devices and the determined physical layer property of the communication channel.

Abstract: A Boost DC-DC switching converter, having a safety protection method for a short circuit to ground during normal Boost operations, is described. A short circuit protection mechanism, to be used at startup, is also described. A low current capability active clamp is activated, during a soft or hard short circuit condition, and an isolation switch is turned off. An input of the switching converter is isolated from an output of the switching converter, and the Boost switching converter is able to safely discharge high energy stored in its coil, with no external components and minimum extra silicon area.

Abstract: A flyback converter is provided that detects a load-transient-produced increase in the output current to more quickly detect and respond to the load transient.

Abstract: A switching converter with improved load transient response is provided, including a panic comparator with a reset switch, a panic latch that is set by an output of the panic comparator and reset in conjunction with a strobe timing, and a timing generator which generates reset and strobe signals. The timing generator may include a gated oscillator, enabled by the panic latch. The panic comparator may include an HPF element, configured to accelerate the panic comparator response. The switching converter may be multi-phase.

Abstract: A flyback converter includes a synchronous rectifier switch transistor controlled by a controller. The controller cycles the synchronous rectifier switch transistor to lower an output voltage by transferring energy from a secondary-side output capacitor to a primary-side input capacitor.

Abstract: A voltage regulator and a corresponding method of regulating a voltage are presented. The voltage regulator includes an N-type power switch, an error amplifier, and a switch capacitor circuit. The switch capacitor circuit includes a first capacitor coupled to a network of switches, the switch capacitor circuit has a first port coupled to an output the error amplifier, a second port coupled to an output terminal of the power switch, and a third port coupled to a control terminal of the power switch. The switch capacitor circuit is iteratively operable between a first phase and a second phase. In the first phase the first port is coupled to ground via a path comprising the first capacitor, and in the second phase the second port is coupled to the third port via a path comprising the first capacitor. The voltage regulator may be implemented as a low dropout regulator.

Abstract: A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.

Abstract: A digital filter for filtering a pulse density modulation (PDM) signal is presented. The filter has a first filter circuit to receive an input signal and to provide a filtered input signal at successive time steps which include a first filtered value at the first time step and a second filtered value at a second time step. The filter also has a quantizer to provide an output signal comprising output values at successive time steps and a filter variable circuit with a first multiplication circuit to receive the first filter variable, and divide the first filter variable by a first gain factor and a first summing circuit configured to receive the divided first filter variable, receive the output signal, and add the divided first filter variable and the first output value and a second multiplication circuit and a delay circuit.

Abstract: An active pull-up circuit which is operated between an upper voltage and a lower voltage and which pulls up an intermediate node to the upper voltage in reaction to an input voltage of the pull-up circuit falling from the upper voltage to an intermediate voltage is described. The pull-up circuit comprises a first transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to the input voltage. The pull-up circuit comprises a second transistor having a source terminal coupled to the upper voltage, a drain terminal coupled to the intermediate node and a gate terminal coupled to a control node. In addition, the pull-up circuit comprises control circuitry configured to pull the control node to a voltage level of the intermediate node, subject to the input voltage falling from the upper voltage to the intermediate voltage.