Abstract: An auto-calibrated current sensing comparator is provided. A secondary dynamic comparator shares the same inputs and acts to adjust a calibration control of the current sensing comparator. The calibration control may be in the form of adjusting the offset of the current sensing comparator or adjusting a propagation delay that is added to its output.

Abstract: A low dropout (LDO) device with improved linear mode comprising an error amplifier, a programmable attenuation factor circuit coupled to said error amplifier, a feedback network whose input is electrically connected to said programmable attenuation factor circuit and whose output is electrically coupled to the negative input of said error amplifier, a high side (HS) pre-drive circuit whose input is a high impedance (HiZ) mode signal, a low side (LS) pre-drive circuit whose input is a low pull-down input mode signal, a high side (HS) output stage element electrically coupled to said high side (HS) pre-drive circuit, a low side (LS) output stage element electrically coupled to said low side (LS) pre-drive circuit, and a high side sense (HSENSE) output stage element whose gate is electrically coupled to said high side (HS) pre-drive circuit, and whose gate and source are electrically connected to the output of said error amplifier.

Abstract: The present disclosure relates to methods and circuits to achieve a buck-boost switching regulator that allows changing operation modes without causing large output ripples during transition of operation modes Increased error amplifier output voltage range over which the converter stays in its present operating mode (buck or boost or buck-boost), resulting in hysteresis between error amplifier output voltage and output voltage). The larger the hysteresis, the smaller will be the likeliness of having to switch between modes. A first embodiment is combining masking logic applied to signals driving the switches of the switching regulator and offset feedback to outputs of the error amplifier in order to providing hysteresis to suppress operation mode bounce and to minimize ripples while a second embodiment is monitoring pulse width of PWM pulses by a pulse width checker.

Abstract: A level shifter does not require any DC (standby) current consumption and has a fast operation with low propagation delay. The level shifting from input to output voltage ranges is performed by a pair of level shifting capacitors. The input-output power voltages domains are unrestricted and flexible. DC isolation is deployed between power domains. Symmetrical rise/fall times are without duty cycle distortion. Over voltage stress is reduced by using metal capacitors. Finally the level shifter does not use high-voltage devices for level shifting purpose. Embodiments of level shifters provide one-way level shifting and bi-directional level shifting.

Abstract: An auto-calibrated current sensing comparator is provided. A secondary dynamic comparator shares the same inputs and acts to adjust a calibration control of the current sensing comparator. The calibration control may be in the form of adjusting the offset of the current sensing comparator or adjusting a propagation delay that is added to its output.

Abstract: A method for the start-up and/or the maintenance of a supply voltage for a driver circuit for a solid state light source is described. The driver circuit comprises a switched-mode power converter with a switch and a transformer. The switched-mode power converter converts an input voltage into an output voltage. The driver circuit has a controller which generates a gate control signal for putting the power converter switch into an on-state or an off-state. The driver circuit comprises a supply voltage capacitor to provide a voltage to the controller. A primary coil of the transformer is arranged in series with the power converter switch. A secondary coil arrangement of the transformer provides the output voltage. and is coupled to the supply voltage capacitor via a supply voltage transistor which is controlled such that the supply voltage provided by the supply voltage capacitor lies within a pre-determined voltage interval.

Abstract: The present document relates to the measurement of the current through a transistor. In particular, the present document relates to a circuit arrangement which allows an accurate measurement of the current through a power transistor. A circuit arrangement is described. The circuit arrangement is configured to provide an indication of a current flowing through a pass switch, when the pass switch is arranged in parallel to the circuit arrangement. The circuit arrangement comprises a matching unit which comprises a switch bank comprising a plurality of parallel reference switches; a resistor bank comprising a plurality of serial reference resistors; and a reference current source configured to provide a reference current flowing through the switch bank and the resistor bank. The resistor bank and the switch bank are arranged in series.

Abstract: The present document relates to power transformers for electronic computing devices. In particular, a power converter configured to convert electrical power at a DC input voltage Vin into electrical power at a DC output voltage is described. The power converter comprises a plurality of flying capacitors, and a plurality of switches which are configured to arrange the plurality of flying capacitors in accordance to a sequence of operation phases. The power converter comprises a control unit configured to control the plurality of switches to repeat the sequence of operation phases at a duty cycle frequency. The plurality of flying capacitors is arranged in series during the operation phases of the sequence of operation phases. The sequence of operation phases comprises at least two operation phases during which the plurality of flying capacitors is arranged in a different order.

Abstract: A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.

Abstract: A power efficient method and system for ensuring a reliable operation of dimmers in conjunction with solid state lighting devices such as LED or OLED assemblies is presented. A controller for a driver circuit of a solid state light bulb assembly is described. The solid state light bulb assembly comprises a solid state light source. The driver circuit comprises a switched-mode power converter. The controller is configured to receive an input voltage indicative of a mains electricity supply submitted to a dimmer; to determine that the dimmer is in an off-phase, based on the input voltage; and, if it is determined that the dimmer is in an off-phase, to generate a control signal for the switched-mode power converter to operate the switched-mode power converter in a switched mode for discharging one or more capacitances at an input of the switched-mode power converter.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required.

Abstract: A low dropout (LDO) device with improved linear mode comprising an error amplifier, a programmable attenuation factor circuit coupled to said error amplifier, a feedback network whose input is electrically connected to said programmable attenuation factor circuit and whose output is electrically coupled to the negative input of said error amplifier, a high side (HS) pre-drive circuit whose input is a high impedance (HiZ) mode signal, a low side (LS) pre-drive circuit whose input is a low pull-down input mode signal, a high side (HS) output stage element electrically coupled to said high side (HS) pre-drive circuit, a low side (LS) output stage element electrically coupled to said low side (LS) pre-drive circuit, and a high side sense (HSENSE) output stage element whose gate is electrically coupled to said high side (HS) pre-drive circuit, and whose gate and source are electrically connected to the output of said error amplifier.

Abstract: An overshoot reduction circuit within a low dropout voltage regulator eliminates an overshoot at an output terminal resulting from a transient fault condition occurring at an input or output terminal. The overshoot reduction circuit monitors to sense if there is a transient fault condition occurring at the input or output terminal and provides a Miller capacitance at the output terminal of a differential amplifier of the low dropout voltage regulator to prevent the output of the differential amplifier from being discharged to ground during the transient. A control loop circuit balances current within an active load of the differential amplifier to clamp the output of the differential amplifier to its normal operating point. When the transient fault condition ends, the output voltage of the differential amplifier is set such that a pass transistor of the low dropout regulator responds quickly to resume the regulation to reduce or eliminate the overshoot.

Abstract: A voltage mirror circuit, having an input node and an output node provides substantially equal voltage levels at the input node and the output node. The voltage mirror circuit comprises an input current source transistor, an input gain transistor arranged in series with the input current source transistor such that the input gain transistor is traversed by the bias current, wherein the voltage level at the input node corresponds to the voltage drop across the input current source transistor and the input gain transistor. An intermediate gain transistor forms a first current mirror with the input gain transistor. An output current source transistor forms a second current mirror with the intermediate current source transistor. The voltage level at the output node corresponds to the voltage drop across the output current source transistor and the output gain transistor.

Abstract: The efficient control of a plurality of high side switches, e.g. the high side switches of half bridges is presented. A control circuit contains a charge provisioning unit to provide an electrical charge. The control circuit contains a plurality of sets of high control switches for the plurality of high side switches, respectively; wherein each set of high control switches is used to arrange the charge provisioning unit in parallel to a gate-source capacitance of the respective high side switch. The control circuit comprises a controller to, during a phase of a plurality of different phases, control a respective set of high control switches from the plurality of sets of high control switches to arrange the charge provisioning unit in parallel to the gate-source capacitance of the respective high side switch from the plurality of high side switches, to switch on the respective high side switch.

Abstract: A circuit is provided with inrush current protection through control of the output current at start-up by a current source that does not rely on the output capacitor and which provides a smooth transition from a controlled current mode during a start-up phase to a voltage regulation mode.

Abstract: Systems and methods for providing a boost converter with an improved stability are disclosed. A sample and hold circuit is connected to the output of the boost converter. That sample and hold circuit holds the output voltage before the main switch of the boost converter turns ON and holds the voltage while the main switch is ON. Thus a high frequency oscillation can be eliminated, an increased control bandwidth without stability problems can be achieved, and no complicated additional circuit is required.

Abstract: A multi-phase DC-to-DC converter is configured to achieve fast transient response and to optimize efficiency over the load range. Phase shedding changes the active number of phases according to output currents. Each phase of the converter has an inductor configured to optimize the efficiency for a range of load currents in which that phase is used. A converter may have 3 phases, the first used only in sleep mode and has a large inductance with low AC losses, the second used in sync mode at low currents and having a lower inductance with low AC losses, the third phase is used in sync mode at high currents and has small inductance with low DC losses. The number of phases is ?2.

Abstract: The present document relates to a start-up circuit comprising a power switch wherein a circuit charges a supply voltage capacitor. The capacitor provides a supply voltage to a power switch; the power switch forms a switched power converter with a power converter network. The circuit comprises a source and gate interface for coupling the circuit to the power switch; a capacitor interface couples the circuit to the supply voltage capacitor; a start-up path couples the gate interface to the capacitor interface; wherein the startup path provides a voltage at the gate interface which is at or above a threshold voltage of the power switch; and a charging path couples the source interface to the capacitor interface; wherein the charging path provides a charging current to the capacitor interface, when the power switch is in on-state.