Abstract: A signal modulator for modulating at least one input signal is disclosed. The modulator includes an adaptive ramp generator receiving a clock signal having a clock cycle. The adaptive ramp generator provides a ramp signal having a profile starting from a minimum level adjusted in each clock cycle. The signal modulator may receive a first, second, and third input signal, and a clock signal. The first and second input signals may derive from a single signal where the second signal is equal to the first signal shifted by 180 degrees. The third signal may be a fixed level that sets the nominal duty cycle of the modulator. The input signal having the highest amplitude among the first, second, and third input signals is identified. The minimum level of the ramp signal is adjusted, and the peak value of the ramp maintained substantially equal to the signal having the highest amplitude.

Abstract: An under-voltage lockout (UVLO) circuit configured for indicating that an electronic device may be enabled and disabled based on threshold levels of a power supply voltage. The UVLO circuit has a non-differential comparator configured to have a fixed threshold voltage. A voltage divider having a first terminal connected to the power supply voltage and configured to adapt a compare signal applied to the non-differential comparator to be proportional the power supply voltage such that a desired threshold voltage for the power supply voltage causes the non-differential comparator to change its output state. The UVLO circuit has a hysteresis controller configured for adjusting the compare voltage such that the power supply voltage has at least two threshold voltages to cause the non-differential comparator to change states. The non-differential comparator comprises a flipped gate transistor with a gate-to-source threshold greater than a normally gated transistor.

Abstract: An apparatus for dynamic range enhancement (DRE) which receives an input signal and provides a DRE output signal is presented. The apparatus has an error correction circuit to apply an error correction factor to the input signal such that the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor. The error correction factor is representative of an error generated by the apparatus.

Abstract: The disclosure provides for a slope voltage compensation circuit with an adaptive slope compensation method, in a DC-DC switching converter operating in current control mode, at duty cycles greater than 50%. The proposed solution allows for the dynamic range of useful operation to be extended, lowering the slope voltage compensation at the beginning of the cycle, and then increasing the compensation as 50% duty cycle is achieved. This method is based on voltage control instead of time, and a second phase of a clock is not required.

Abstract: A switched power converter and a method are presented. The converter has a main stage with a main converter that exhibits an inductor and at least one switch to control an inductor current through the inductor. Furthermore, the switched power converter has an auxiliary stage to determine a sensed current indicative of the inductor current, and to provide or sink an auxiliary current to or from the output node, wherein the auxiliary current depends on the sensed current. In addition, the switched power converter has control circuitry to determine whether the output voltage falls below an undershoot threshold or exceeds an overshoot threshold, and to activate the auxiliary stage to provide or sink the auxiliary current, if it is determined that the output voltage falls below the undershoot threshold or exceeds the overshoot threshold.

Abstract: The clock input of a buck converter is delayed, and the delay is controlled proportionally to the preceding high-side output switch on time. In the steady state, the high-side switch on time is uniform, and the clock is offset by a fixed amount. When sub-harmonic oscillation begins to occur, the high-side switch on time may increase during a cycle. The longer high-side on time causes the clock to be delayed by an increased amount. This has the effect of increasing the following low-side output switch on time. This further increases the subsequent high-side on time, and counteracts the effects of sub-harmonic oscillation. If the system is properly controlled, loop compensation is implemented correctly and sub-harmonic oscillation is prevented. In addition, the scheme may also be configured for the delay to be controlled proportionally to the preceding low-side output switch on time of the buck converter.

Abstract: The present document discloses a circuitry for delaying a digital input signal. In particular, the circuitry may comprise a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The delay cell circuit may be coupled to the reciprocal current DAC. More particularly, the reciprocal current DAC may be configured to output a charge current to the delay cell circuit according to a value of a control input provided to the reciprocal current DAC. The charge current output by the reciprocal current DAC may be inversely proportional to the value of the control input, wherein the delay depends on the charge current.

Abstract: A high-voltage power converter with a high-side switch coupled with a high-voltage input and a high-side switch control coupled with the high-side switch are presented. The high-side switch control drives the high-side switch on and off. There is a low-side switch coupled via an output node to the high-side switch. The low-side switch is on when the high-side switch is off and vice versa. A supply capacitor is coupled with a low-voltage supply terminal. The high-side switch control to provides a supply voltage for the high-side switch control. A communication module is coupled with the high-side switch control to provide a bidirectional communication between the high-side switch control and a control system that operates in a low-voltage domain, wherein the communication to and from the high-side switch control is enabled when the low-side switch is on and the high-side switch is off.

Abstract: A method and associated system have been proposed to achieve power savings in PWM DACs by truncating PWM sequences and maximizing the amount of time available to power up a DAC cell without sacrificing sensitivity to element mismatch. The DAC circuit includes a driver to receive a digital input and to provide a plurality of drive sequences, a digital-to-analog converter, and a controller. The digital-to-analog converter includes an array of digital-to-analog elements operable over several time steps. Upon identifying that the digital signal is below a threshold value, the controller is configured to shorten the drive sequences; and for each time step to identify a first set of elements and a second set of elements among the array of digital-to-analog elements; to apply the shortened drive sequences to the first set; to disable the second set; and to shift the first set and the second set by one element.

Abstract: A voltage proportional to a pulse width modulation (PWM) duty cycle is generated, using a low pass filter (LPF). A 2nd or higher order LPF is provided, giving a 90×(2n+1) degree phase shift for (n=0, 1, 2, . . . ), so that the sampling timing at the latter stages can be at the rising and/or falling edge of the PWM input signal. A switched capacitor circuit after the 2nd or higher order LPF is provided, removing a voltage ripple on an LPF output, and using a smaller device area.

Abstract: An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by means of a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.

Abstract: A hybrid power converter and a method with low power losses over an extended conversion range are presented. The converter maintains low conversion losses associated with reduced inductor ripples not only for a single conversion ratio, but over a wide range of conversion ratios. The power converter has a ground terminal, an input terminal for receiving an input voltage and an output terminal for providing an output voltage with a target conversion ratio. The power converter has an inductor; a first flying capacitor selectively coupled to the inductor; a second flying capacitor selectively coupled to the inductor; a network of switches; and a driver adapted to operate the converter in a first mode associated with a first range of conversion ratios.

Abstract: A charge pump controller for controlling a charge pump adapted to convert an input voltage into an output voltage with a conversion ratio is presented. The charge pump is operable in a plurality of modes corresponding to different conversion ratios. The controller includes a first selector for selecting a mode of operation of the charge pump. The first selector comprises a first input for coupling to a voltage supply; and a second input for coupling to a source signal. The first selector identifies a target value of the output voltage. The selector calculates a product of the conversion ratio and the input voltage. The selector compares the product with the target value and selects a mode of operation of the charge pump by increasing or decreasing the conversion ratio based on the comparison. The selector maintains the conversion ratio for a length of time before decreasing the conversion ratio.

Abstract: A power converter comprises a high side switching element and a low side switching element arranged in series between an input terminal of the power converter and a reference terminal. A first feedback circuit of the power converter is configured to control an output voltage or an output current at an output terminal of the power converter. The first feedback circuit comprises a first comparator configured to generate a first control signal for controlling the switching of the switching elements by comparing a first error voltage with a first ramp signal. A second feedback circuit of the power converter is also configured to control said output voltage or said output current. The second feedback circuit comprises a second comparator configured to generate a second control signal by comparing a second error voltage with a second ramp signal.

Abstract: The proposed Power Management Integrated Circuit (PMIC) features the option to synchronize the charge-pump of a PMIC with the system clock, and then to swap and self-oscillate and skip pulses, when the digital controls of the PMIC send a first order to the charge-pump. The clock control circuitry of the PMIC also features the option for the charge-pump to then swap and use the system clock again, when the digital controls of the PMIC send a second order to the charge-pump. The designed transition of the clock from clock sync-mode to self-oscillate, and from self-oscillate back to clock sync-mode, does not present any phase discontinuity.

Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

Abstract: The present disclosure provides a DC-DC switching converter architecture that utilizes the chip's thermal capacity effectively by implementing adaptive switching frequency scaling over the operation region, keeping the die/package temperature constant. The power budget is effectively utilized, and the external components such as capacitors, inductors, and pass device sizes are reduced, thereby increasing the efficiency of the switching converter. An adaptive frequency scalar is optimized, avoiding losses, especially at high loads. The larger the input and output voltage ranges, the bigger the benefit the disclosure becomes.

Abstract: A multi-level power converter and method are presented. The converter provides a ground terminal, an input terminal and an output terminal. It also provides an inductor, a first flying capacitor, a second flying capacitor and a network of switches. The network of switches is driven with a sequence of states including a first state and a second state. In the first state one of the input terminal and the ground terminal is coupled to the output terminal via a first path containing the first flying capacitor and which bypasses the inductor, while the remaining terminal among the input terminal and the ground terminal is coupled to the output terminal via a second path containing the second flying capacitor and the inductor.

Abstract: A switching converter with reduced dead-time and without reverse-recovery is disclosed. The switching converter includes a first power switch coupled to a second power switch, a mode detector and a controller. The mode detector is adapted to detect a mode of operation of the first power switch and the second power switch, and to identify a first period during which the first power switch is turned on and operates in a linear mode while the second power switch is turned off. The controller is adapted to bias the second power switch with a predetermined voltage during the first period to turn on the second power switch during a second period. In the second period the first power switch is operating in a saturation mode.

Abstract: A charge pump controller for controlling a charge pump adapted to convert an input voltage into an output voltage with a conversion ratio is presented. The charge pump is operable in a plurality of modes corresponding to different conversion ratios. The controller includes a first selector for selecting a mode of operation of the charge pump. The first selector comprises a first input for coupling to a voltage supply; and a second input for coupling to a source signal. The first selector identifies a target value of the output voltage. The selector calculates a product of the conversion ratio and the input voltage. The selector compares the product with the target value and selects a mode of operation of the charge pump by increasing or decreasing the conversion ratio based on the comparison. The selector maintains the conversion ratio for a length of time before decreasing the conversion ratio.