Abstract: A power system and related methods provide sense resistor fault detection and safe operation of switching power converters and connected devices such as portable electronic devices powered by the switching power converter. The power system detects an open circuit or short circuit condition of the sense resistor and controls output current of the switching power converter to ensure safe operating conditions of the power system and connected equipment. The power system can also detect initial inrush current of the connected equipment and detect a duty cycle of the switching power converter to positively detect a short circuit condition of the sense resistor.

Abstract: An under-voltage lockout (UVLO) circuit configured for indicating that an electronic device may be enabled and disabled based on threshold levels of a power supply voltage. The UVLO circuit has a non-differential comparator configured to have a fixed threshold voltage. A voltage divider having a first terminal connected to the power supply voltage and configured to adapt a compare signal applied to the non-differential comparator to be proportional the power supply voltage such that a desired threshold voltage for the power supply voltage causes the non-differential comparator to change its output state. The UVLO circuit has a hysteresis controller configured for adjusting the compare voltage such that the power supply voltage has at least two threshold voltages to cause the non-differential comparator to change states. The non-differential comparator comprises a flipped gate transistor with a gate-to-source threshold greater than a normally gated transistor.

Abstract: An apparatus for dynamic range enhancement (DRE) which receives an input signal and provides a DRE output signal is presented. The apparatus has an error correction circuit to apply an error correction factor to the input signal such that the DRE output signal provided by the apparatus is dependent on the input signal and the error correction factor. The error correction factor is representative of an error generated by the apparatus.

Abstract: A method of communication in a Bluetooth Low Energy network is presented. The network has a master device and a plurality of slave devices between a first slave device and a second slave device. The method steps include: sending from the master device to the first slave device a synchronisation delay parameter; and sending from the master device to the second slave device the synchronisation delay parameter and a relative offset parameter. At the second slave device, the method steps include determining a synchronisation time point by adding the relative offset parameter to the synchronisation delay parameter. At the synchronisation time point, the method steps include waking the first and second slave devices and sending a communication from the first slave device to the second slave device.

Abstract: A quantizer and a method for a sigma-delta modulator circuit that may be used as a component within an adaptive-noise cancelling headphone are presented. An apparatus includes a quantizer to receive an input signal with successive input values and quantizes the input signal at discrete intervals. This is done by mapping the input value of the input signal at each interval to one of a plurality of quantization levels with three or more quantization levels that are non-uniformly spaced. The plurality of quantization levels has a first portion with two or more quantization levels having the same sign and being proportional to a first fraction having one as its numerator and two to a power of a first variable as its denominator, the first variable being an integer and having a different value for each of the two or more quantization levels of the first portion.

Abstract: A signal modulator for modulating at least one input signal is disclosed. The modulator includes an adaptive ramp generator receiving a clock signal having a clock cycle. The adaptive ramp generator provides a ramp signal having a profile starting from a minimum level adjusted in each clock cycle. The signal modulator may receive a first, second, and third input signal, and a clock signal. The first and second input signals may derive from a single signal where the second signal is equal to the first signal shifted by 180 degrees. The third signal may be a fixed level that sets the nominal duty cycle of the modulator. The input signal having the highest amplitude among the first, second, and third input signals is identified. The minimum level of the ramp signal is adjusted, and the peak value of the ramp maintained substantially equal to the signal having the highest amplitude.

Abstract: A flyback converter control architecture is provided in which primary-only feedback techniques are used to ensure smooth startup and detection of fault conditions. During steady-state operation, secondary-side regulation is employed. In addition, current limits are monitored during steady-state operation using primary-only feedback techniques to obviate the need for a secondary-side current sense resistor.

Abstract: A flyback converter controller is provided with secondary-side controller that adjusts a discharge current form an output voltage rail during a communication period with a primary-side controller to maintain the output voltage within regulation.

Abstract: A radio frequency input/output circuit with a composite inductor structure is presented. The composite inductor structure has a plurality of inductors that are interwound. The composite inductor structure is implemented on a chip. The plurality of inductors are magnetically coupled. The plurality of inductors are interwound around a core. A second inductor is coupled in series with a first inductor and the first inductor is coupled in series with the third inductor. The first inductor and the third inductor are coupled at a centre tap, such that the first inductor and the third inductor form a centre-tapped coil. The centre tap is coupled to an input terminal.

Abstract: A voltage regulator and a method for generating a retention voltage for a RAM cell that is sufficiently high to prevent data loss, while minimizing leakage currents are presented. The A voltage regulator is used for generating at least one voltage. The regulator contains mirror circuitry, a leakage device coupled to the mirror circuitry, and a first resistive device coupled to the mirror circuitry via a first output node. The mirror circuitry mirrors a leakage current from the leakage device to the first resistive device, and the leakage current contributes to the generation of a first reference voltage at the first output node.

Abstract: A switching power supply controller for a switching power supply is provided that measures an input voltage through an application of a load during an input voltage measurement period following connection of the switching power supply to an AC mains. Based upon the measured input voltage, the controller adjusts a start-up delay period so that the start-up delay period is substantially constant despite variations in an AC line voltage for the AC mains.

Abstract: A switched power converter and a method are presented. The converter has a main stage with a main converter that exhibits an inductor and at least one switch to control an inductor current through the inductor. Furthermore, the switched power converter has an auxiliary stage to determine a sensed current indicative of the inductor current, and to provide or sink an auxiliary current to or from the output node, wherein the auxiliary current depends on the sensed current. In addition, the switched power converter has control circuitry to determine whether the output voltage falls below an undershoot threshold or exceeds an overshoot threshold, and to activate the auxiliary stage to provide or sink the auxiliary current, if it is determined that the output voltage falls below the undershoot threshold or exceeds the overshoot threshold.

Abstract: The disclosure provides for a slope voltage compensation circuit with an adaptive slope compensation method, in a DC-DC switching converter operating in current control mode, at duty cycles greater than 50%. The proposed solution allows for the dynamic range of useful operation to be extended, lowering the slope voltage compensation at the beginning of the cycle, and then increasing the compensation as 50% duty cycle is achieved. This method is based on voltage control instead of time, and a second phase of a clock is not required.

Abstract: A system for improving a power factor (PF) of a power converter in signal communication with a rectifier and an electromagnetic interference capacitor is disclosed. The system includes a controller and a threshold detector. The threshold detector is configured to measure and compare a rectified voltage against a threshold voltage and the controller is configured to set the power converter to a stop-mode. The power converter is set to the stop-mode at a stop-time that is less than a first zero-crossing time. The controller is further configured to set the power converter to a run-mode at a time that is past the first zero-crossing time.

Abstract: A terminal includes a first storage, which is kept turned on in a sleep mode, and is utilized to store a first packet transmitted with a server, a second storage which is utilized to store data required for the terminal in a wake-up mode, a central processing unit which is utilized to generated a second packet according the first packet and send the first packet to a access point in the sleep mode, and a communication unit which is connected to the access point and is utilized to transmit the second packet according to control of the central processing unit.

Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.

Abstract: The clock input of a buck converter is delayed, and the delay is controlled proportionally to the preceding high-side output switch on time. In the steady state, the high-side switch on time is uniform, and the clock is offset by a fixed amount. When sub-harmonic oscillation begins to occur, the high-side switch on time may increase during a cycle. The longer high-side on time causes the clock to be delayed by an increased amount. This has the effect of increasing the following low-side output switch on time. This further increases the subsequent high-side on time, and counteracts the effects of sub-harmonic oscillation. If the system is properly controlled, loop compensation is implemented correctly and sub-harmonic oscillation is prevented. In addition, the scheme may also be configured for the delay to be controlled proportionally to the preceding low-side output switch on time of the buck converter.

Abstract: The present document discloses a circuitry for delaying a digital input signal. In particular, the circuitry may comprise a delay cell circuit and a reciprocal current digital-to-analog converter (DAC). The delay cell circuit may be coupled to the reciprocal current DAC. More particularly, the reciprocal current DAC may be configured to output a charge current to the delay cell circuit according to a value of a control input provided to the reciprocal current DAC. The charge current output by the reciprocal current DAC may be inversely proportional to the value of the control input, wherein the delay depends on the charge current.

Abstract: A high-voltage power converter with a high-side switch coupled with a high-voltage input and a high-side switch control coupled with the high-side switch are presented. The high-side switch control drives the high-side switch on and off. There is a low-side switch coupled via an output node to the high-side switch. The low-side switch is on when the high-side switch is off and vice versa. A supply capacitor is coupled with a low-voltage supply terminal. The high-side switch control to provides a supply voltage for the high-side switch control. A communication module is coupled with the high-side switch control to provide a bidirectional communication between the high-side switch control and a control system that operates in a low-voltage domain, wherein the communication to and from the high-side switch control is enabled when the low-side switch is on and the high-side switch is off.

Abstract: A frequency divider unit to receive an oscillating signal and to update, at an output of the frequency divider unit, a frequency-divided oscillating signal is presented. The frequency divider unit has a first clocked signal inverter to update, clocked based on the oscillating signal, a first intermediate signal at an output of the first clocked signal inverter. The frequency divider unit has a second clocked signal inverter, wherein the output of the first clocked signal inverter may be connected to an input of the second clocked signal inverter, and wherein the second clocked signal inverter updates, clocked based on the oscillating signal, a second intermediate signal at an output of the second clocked signal inverter. The frequency divider unit has a continuously operating signal inverter coupled between the output of the second clocked signal inverter and the input of the first clocked signal inverter.