Abstract: A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.

Abstract: An insulated gate field-effect transistor or similar semiconductor-insulator-semiconductor structure has an increased time-dependent dielectric failure lifetime due to a reduction in the field across the gate insulator. The electric field in the gate insulator is reduced without degrading device performance by limiting the field only when the gate voltage exceeds its nominal range. The field is limited by lowering the impurity concentration in a polysilicon gate electrode so that the voltage drop across the gate insulator is reduced. In order to avoid degrading the device performance when the device is operating with nominal voltage levels, a fixed charge is imposed at the interface between the gate electrode and the gate insulator, so at a gate voltage of about the supply voltage level the response changes to exhibit less increase in the drop across the gate insulator for higher voltages.

Abstract: A method and associated structures for creating and implementing applications using function-objects, wherein each function to be performed by an application is embodied in a "function-object" that can adapt itself to various devices or interfaces that it encounters. Program designers can mix and match routines such as input and output routines by setting variants of a function-object.

Abstract: In a pipelined digital computer, an instruction decoder decodes register specifiers from multiple instructions, and stores them in a source queue and a destination queue. An execution unit successively obtains source specifiers of an instruction from the source queue, initiates an operation upon the source specifiers, reads a destination specifier from the destination queue, and retires the result at the specified destination. Read-after-write conflicts may occur because the execution unit may overlap execution of a plurality of instructions. Just prior to beginning execution of a current instruction, the destination queue is checked for conflict between the source specifiers of the current instruction and the destination specifiers of previously issued but not yet retired instructions. When an instruction is issued for execution, its destination specifiers in the destination queue are marked to indicate that they are associated with an executed but not yet retired instruction.

Abstract: Transformers (T1, T2), switches (M1) and (M2), rectifiers (DR1, DR2, DR3, DR4) and low-pass filter (LF, CF) form a basic power train circuit (12). Auxiliary switches (A1, A2), diodes (DS1, DS2) and capacitors (CS1, CS2) form active clamp circuit (10). The capacitances for (CS1, CS2) are chosen large enough such that the voltages (vCS1, vCS2) across the capacitors are essentially constant during several switching cycles. Switches (M1) and (A1) are driven by the signal (V.sub.G1), while switches (M2) and (A2) are driven by (V.sub.G2). When (M1) is turned OFF, the energies stored in the magnetizing and leakage inductances in (T1) will resonate with the output capacitance of (M1) first. When the voltage (V.sub.M1) across (M1) exceeds the voltage (V.sub.CS1) across (CS1), (DS1) conducts and (V.sub.M1) is clamped at (V.sub. CS1), which has a steady-state value of slightly less than two times the input voltage (E). During this interval, the capacitor (CS1) is charged by the leakage inductor current (i.sub.LK1).

Abstract: An expert system for determining the likelihood of failure of a unit in a computer system. The operating system of the computer system maintains a log of the errors occurring for each unit in the computer system. If a predetermine number of errors have been entered in the log for a specific unit, the expert system retrieves the error entries relating to that unit and processes them to determine whether a failure is likely to occur. In this, the processing performed by the expert system is arranged so that tests relating to components of increasing particularity, and decreasing generality, are performed after the tests relating to more general components.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: According to a first aspect of the invention, a DASUM (Durable Atomic Storage Update Manager) provides an extensible framework assuring complex changes to persistent storage of data within a computer system, including a distributed computer system. During normal runtime, modifications to permanent storage are broken down and organized as a plurality of simpler transactions. These simpler transactions are accomplished atomically by executing associated agents within the computer program under execution. Each agent need only have the ability to complete its own process, and need not be able to deal with side effects from other transactions. Without needing to know what steps may be required, each agent supplies three agent-specific procedures that can be called during recovery from a fault. The DASUM provides seven services that, during normal transaction execution, can store information in a logger necessary for recovery from a fault.

Abstract: A method and apparatus is provided for use in an asynchronous bus interface capable of multiple or single width transfers and controlled by handshake signals, in which the bus transaction may include multiple successive data transfers delineated by a data strobe, and in which each data transfer is terminated by a data handshake signal, and in which data transfers for different cycle types incur different propagation delays, including bus buffering apparatus for directing transfers over single and multiple width busses, and an asynchronous bus controller for returning data handshake signals with individualized timing characteristics in response to the master data strobe and the cycle type of the transaction, such that each successive data transfer is completed in the minimum time that propagation delays, as indicated by the cycle type, will allow, in order to maximize bus throughput.

Abstract: A direct memory access controller (DMAC) is provided to transfer bytes from arbitrary offset byte boundaries while performing data check operations in parallel to the movement of data in parallel through the DMA controller. The DMA controller moves data during each memory cycle and validates the moved data at the destination memory during the writing of bytes to the destination address.

Abstract: A color information storage and processing system including a converter adapted to translate red, green and blue values of a color into an achromatic dimension and two chromatic dimensions. The red, green and blue values are processed to provide chromatic dimensions which are independent from one another and completely decoupled from the achromatic dimension. The color information storage and processing system stores the achromatic and chromatic dimensions and performs image processing utilizing the stored dimensions. A decoder translates the achromatic and chromatic dimensions back into red, green and blue values for use in the operation of a color monitor.

Abstract: An equipment cabinet employs a rack-mountable equipment enclosure surrounded by a base, a cap, and front and rear covers. Each cover consists of a bezel and a door reversibly mounted thereon via removable hinge pins. The bezels have sidewalls that rest against ledges on the edges of the enclosure to receive support therefrom. The door has a centrally-located latch, the latch having a pawl with an eccentric catch portion that engages a latch opening on a ledge extending from the bezel. The pawl also has a tab that rests between the ends of an arcuate raised portion on the rear of the door to limit the rotational travel of the pawl. The base, cap, and covers are configured so that the enclosure is surrounded by hollows forming a peripheral passageway for cabling and the like. The base and cap have front and rear handle-like projections through which cables may be routed, and the covers have inward-facing snap tabs that engage the handle-like projections to secure the covers to the base and cap.

Abstract: The objects stored in computer's memory include a directed graph of object directories. Each object directory stores object names and object pointers for locating and accessing other objects. A root directory object, which is the starting point for locating any specified object, stores object names and object pointers to a set of first level object directories. Each object has an associated pathname that defines a path through the directed graph of object directories for accessing that object. More particularly, each pathname is a succession of path elements, proceeding from a first path element to a last path element. A default pathname parsing procedure is used for parsing any specified object's pathname, starting with said first path element, until the default pathname parsing procedure accesses an object directory having its own distinct pathname parsing procedure.

Abstract: A method for determining whether multiple representations of a design of a circuit are consistent with each other, where the circuit includes multiple devices with channels for conducting electrical current. Each representations includes a list of device elements that describe the devices and node elements that describe the nodes which interconnect the devices. The method includes modifying each of the lists by: (1) analyzing the device elements and the node elements to identify at least one channel connected region of said circuit (where a channel connected region includes the subset of the devices that have channels interconnected by a subset of the nodes), (2) defining, for each channel connected region, a channel connected region element that describes the subset of the devices and the subset of the nodes in the region, and (3) replacing the device elements of each subset of devices and the node elements of each subset of nodes in the lists with the channel connected region elements.

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: A method of testing a memory containing data being used by a processor uses a dedicated diagnostic test page (DTP) and diagnostic status page (DSP) in the memory under test to carry out the testing. The DTP is address-tested and pattern-tested first. Then, each page of the memory is in turn copied to the DTP, tested, and then restored from the DTP. During the test, the address of the page being tested is stored in the DSP along with a valid flag and an error detection code (EDC). A recovery procedure uses the information on the DSP to restore memory pages if the test is interrupted.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell a the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: Cooperative patterns are formed in stencils and/or substrates that facilitate the monitoring and control of the circuit assembly process. A pattern of successively-larger etch blocks receives a corresponding pattern of same-size solder blocks; solder reflow problems are indicated when either too many or too few etch blocks are completely covered by solder after reflow. A pattern of same-size etch blocks receives a corresponding pattern of successively-larger solder blocks; problems with solder stencil clogging are indicated when smaller ones of the etch blocks do not receive solder paste during stenciling. Finally, component beacon openings or translucent areas are made in the electronics assembly at component locations. After component placement, the board is appropriately lit, and any uncovered openings indicate missing or grossly misaligned components.

Abstract: A controller for a communication system having a plurality of networks and a plurality of stations communicating with each other by sending messages from a source station to a destination station is disclosed. A plurality of stations may be assigned to a group. A communication history for the stations is determined, where the history corresponds to the messages communicated. The stations are connected into a common network in accordance with the communication history. The communication history corrresponds to a series of packets and is based on a source address and a destination address of each of the packets. A station may have a matrix, the matrix having rows indexed by source system address and columns indexed by destination system address, for storing a value indicating a quantity of information transferred from each station to each other station.

Abstract: In a method and system for monitoring the performance of servers across a network and for suggesting an appropriate server to a client requesting a service, a plurality of probes are placed in various clients in the network by a Broker-Performance Mechanism. The probes request that the servers perform various network functions and measure the response times of the servers in satisfying those requests. The Broker-Performance Mechanism retrieves, analyzes, and stores the response time data. The stored data can be made available to a user for system diagnostic purposes. In addition, when a particular client requests a particular service, the Broker-Performance Mechanism examines the analyzed data and determines which server is best suited, at that particular time, to provide the requested service to the requesting client.