Abstract: An audio speaker system includes: an amplifier, where a positive input terminal of the amplifier is configured to be coupled to a first reference voltage node; and a piezo diaphragm including: a metal plate; a first piezo film attached to the metal plate, where the first piezo film is configured to function as a speaker during operation of the audio speaker system; and a second piezo film attached to the metal plate and spaced apart from the first piezo film, where the second piezo film is configured to function as a microphone during operation of the audio speaker system, where an output terminal of the amplifier is coupled to the first piezo film, and where a negative input terminal of the amplifier is coupled to the second piezo film.

Abstract: A switching power supply includes a secondary control circuit coupled to a secondary side of a transformer of the switching power supply, and a primary control circuit coupled to a primary side of the transformer. The secondary control circuit is configured to receive a power request signal of a load device, and encode the power request signal to generate encoded information. The primary control circuit is configured to receive, by use of the transformer, a feedback signal reflecting an output voltage of the switching power supply, decode the encoded information based on a change of the feedback signal, and based thereon, control the switching power supply to supply power to the load device.

Abstract: A connector for connecting a gas pipe and a heating component of a wire bonder includes a first connection end for connecting the connector to the heating component, and a second connection end for connecting the connector to the gas pipe. A heat-insulation tube is connected between the first connection end and the second connection end. The heat-insulation tube is made of a heat-insulation material and configured to insulate or reduce heat transfer between the first connection end and the second connection end. The connector may further include a first fastening sleeve for fastening the connection between the first connection end and the heat-insulation tube, and a second fastening sleeve for fastening the connection between the second connection end and the heat-insulation tube.

Abstract: A semiconductor molding system is provided that includes a molding device, an image collection device, and a controller connected to the molding device and the image collection device. The image collection device is configured to obtain a target image of a to-be-molded lead frame before the to-be-molded lead frame is molded by the molding device. The controller is configured to determine whether foreign object(s) exist in a non-molding area of the to-be-molded lead frame based on the target image of the to-be-molded lead frame and a reference image. A method for detecting foreign objects of a to-be-molded lead frame is also provided.

Abstract: An inverse voltage-to-current conversion circuit for providing a current that is inversely related to an input voltage of a protected device is disclosed. A first input terminal for receiving a first input voltage signal and a second input terminal for receiving a second input voltage signal. A voltage-to-time converter circuit provides a time indicator pulse signal with a pulse width related to inverse of a difference between the first and second input voltage signals. A time-to-voltage converter circuit provides a voltage indicator signal having a magnitude based on the pulse width of the time indicator pulse signal. A voltage-to-current converter circuit provides a current indicator signal having a magnitude proportional to the voltage indicator signal and inversely related to the difference between the first and second input voltage signals.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.

Abstract: An apparatus includes a reference current generation circuit coupled between a first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current, a first reference current path comprising a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path, a load current path comprising a power switch, and a pulse width modulation (PWM) deglitch circuit configured to control the first switch so as to reduce an overshoot occurring at a leading-edge of a load current flowing through the power switch.

Abstract: A lead frame includes a base comprising a bearing surface for bearing a chip. The bearing surface includes a soldering region, with a solder layer arranged in the soldering region. The solder layer is configured for fixing the chip on the bearing surface. The lead frame includes a groove provided on the bearing surface in a thickness direction of the base. The groove is located outside the soldering region and surrounds at least part of the soldering region along the outer periphery of the soldering region for receiving solder paste overflowed from the soldering region. A depth of the groove is based on a thickness of the base. A packaging structure including the lead frame and a packaging method using the lead frame are also provided.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: A method for calibrating a tray shield used for holding a wafer for processing is provided. The tray shield is in a ring shape. The method includes determining whether a first calibration ring is placeable into an inner chamber of the tray shield. When the first calibration ring is placeable into the inner chamber, the tray shield is determined to be usable for wafer processing. The first calibration ring is moved around inside the inner chamber to remove metal particles or burrs on the inner chamber, and thereafter, a wafer is loaded in the inner chamber. When the first calibration ring is not placeable into the inner chamber, the tray shield may be discarded. The method may also include assembling the tray shield utilizing a second calibration ring having an outer diameter equal to an inner diameter of the ring shape.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path comprises a controllable switch and a first resistive device connected in series between the capacitive device and the gate of the high-side switch, and a control switch connected between the gate of the high-side switch and ground.

Abstract: An equalizer stage circuit includes a first transistor and a second transistor disposed in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes: a first terminal coupled to an emitter or a source of the first transistor; a second terminal coupled to an emitter or a source of the second transistor; a high-frequency portion comprising a first plurality of high-frequency RC time constant members connected in parallel between the first terminal and the second terminal; a first capacitor coupled to the first terminal; a second capacitor coupled to the second terminal; and a low-frequency portion comprising a second plurality of low-frequency RC time constant members connected between the first capacitor and the second capacitor.

Abstract: An apparatus includes a secondary controller coupled to a secondary circuit of a power conversion system, and a primary controller coupled to a primary circuit of the power conversion system, the primary controller being coupled to the secondary controller through an isolation interface, wherein the secondary controller is configured to detect whether a load is coupled to the power conversion system, in response to the load being disconnected from the power conversion system, communicate with the primary controller through pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time, provide a high impedance at the secondary feedback node to reduce power consumption, and in response to the load being reconnected to the power conversion system, communicate with the primary controller through pulling down the secondary feedback node in the secondary circuit for a second predetermined time.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path comprises a controllable switch and a first resistive device coupled in parallel between the capacitive device and the gate of the high-side switch, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A leadframe includes a peripheral frame, a plurality of lead pads, and a die attach pad (DAP). Each lead pad is physically connected to the peripheral frame by a respective connecting portion. The DAP is surrounded by the plurality of lead pads. The DAP includes a first protruding portion coupled to a first lead pad on a first side of the DAP and a second protruding portion coupled to a second lead pad on a second side of the DAP opposite the first side. The DAP does not comprise direct connections to the peripheral frame. The leadframe further includes two or more of the lead pads disposed on either side of the first lead pad on the first side of the DAP; and two or more of the lead pads disposed on either side of the second lead pad on the second side of the DAP.

Abstract: The disclosure provides a semiconductor package having an isolation structure comprising an isolation trench filled with dielectric material, where the isolation structure traverses the thickness of the isolated semiconductor dies.

Abstract: An apparatus includes a first inverter having an input terminal and an output terminal, a first capacitive device connected between the input terminal and the output terminal of the first inverter, and a resistor network coupled to the first capacitive device, wherein the first inverter is configured as a negative amplifier, and the first capacitive device and the resistor network are configured to determine a frequency of an oscillator.

Abstract: A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.

Abstract: A power factor correction (PFC) converter comprises an inductor, a main switch, a voltage divider, a diode, and a controller. The main switch controls the inductor performing magnetization and demagnetization, wherein a voltage difference between two ends of the main switch is a switch voltage. The voltage divider divides the switch voltage and generates a division voltage. The controller performs the following operations periodically in general mode: turning on the main switch; turning off the main switch after the main switch is turned on for a period of time; obtaining the switch voltage according to the division voltage, and determining the period of time for which the main switch is turned on next time according to the switch voltage and a predetermined output voltage of the PFC converter; and obtaining an output voltage according to the switch voltage during a period of time after the main switch is turned off.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.