Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A bootstrap diode circuit includes an anode for coupling to a power supply voltage terminal and a cathode for coupling to a bootstrap voltage terminal. The bootstrap diode circuit also includes a high-voltage p-type metal-oxide-semiconductor (PMOS) transistor, having a source forming the cathode of the bootstrap diode circuit and a drain forming the anode of the bootstrap diode circuit. The high-voltage PMOS transistor has a breakdown voltage higher in magnitude than a voltage drop between a maximum bootstrap voltage and the power supply voltage.

Abstract: A semiconductor device with reduced device resistance is disclosed. The semiconductor device comprises a semiconductor chip in which the chip thickness at the center portion of the chip where the circuit elements are disposed is uniform and is different from the chip thickness near the chip sides distant from the circuit elements.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: A method for controlling a power converter includes turning on a power switch to maintain a desired output voltage, wherein the power switch is coupled to a primary winding to control a primary current flow and the output voltage is provided by a secondary winding. The method also includes adding a capacitance in parallel to the power switch at a time determined by a magnitude of an input voltage to the power converter. Here, the timing of adding the capacitance depends on the operation mode of the power controller. In a low input voltage mode, the capacitance is added in a demagnetization-time during which the secondary winding discharges. In a high input voltage mode, the capacitance is added in a discontinuous time.

Abstract: Clock and data recovery for high-speed serial data protocols is enabled using circuitry that combines the functionality of a decision feedback equalizer with that of a phase detector.

Abstract: A semiconductor Schottky rectifier built in an epitaxial semiconductor layer over a substrate has an anode structure and a cathode structure extending from the surface of the epitaxial layer. The cathode contact structure has a trench structure near the epi-layer and a vertical sidewall surface covered with a gate oxide layer. The cathode structure further comprises a polysilicon element adjacent to the gate oxide layer.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: The structure of a field-effect transistor with a source-down configuration and process of making the transistor are described in this paper. The transistor is built in a semiconductor chip with a trench extending from top chip surface towards the bottom surface. The trench contains a conductive gate material embedded in a dielectric material in the trench. A conductive field plate is also embedded in the trench and extends from the top surface of the chip towards the bottom surface of the chip and splits the conductive gate electrode into two halves. The conductive field plate penetrates the trench and makes electrical contact with the heavily doped substrate near the bottom surface of the chip.

Abstract: A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.

Abstract: A power converter includes a power switch controlling current flow in the power converter and a variable capacitance coupled in parallel to the power switch. The variable capacitance is configured to add a frequency jitter to the power converter.

Abstract: A battery charger controller is configured to add a compensation current in the feedback control loop such that the output voltage varies with the output current to compensate charging cable voltage drop. In some embodiments, the output voltage is also proportional to a compensation resistor. Therefore, cable voltage drop compensation can be adjusted using a resistor that is external to the controller IC. The external resistor may be one of the feedback resistors connected at a voltage feedback pin. In another embodiment, the adjustable resistor is the resistor between the feedback resistors and the voltage feedback pin. In still another embodiment, the adjustable resistor is the resistor in parallel with a compensation capacitor. In embodiments of the invention, adjusting the resistance of the external compensation resistor can change the voltage drop compensation and allow the power supply to meet requirements of different charging cable applications.

Abstract: A hub device enables the deployment of I2C devices in a system that also includes I3C devices. The hub has an I3C-compliant interface with which it communicates with an I3C master(s) on an I3C bus, an I2C-compliant interface with which it communicates with I2C devices on an I2C bus, and logic and memory that supports the conversion between the two domains.

Abstract: A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.

Abstract: A Quasi-Resonant (QR) converter includes a power switch controlling the primary current flow and a time-varying capacitance coupled in parallel to the power switch. The time-varying capacitance is configured to add a frequency jitter to the frequency switch of the converter.

Abstract: In a power supply having a control circuit for regulating the power supply output and a load switch for connecting the output to a load device, a method for reducing standby power includes determining if a load device is connected to the power supply. If no load device is connected, the load switch is turned off, and the power supply enters a standby mode, which includes alternating first time period of power-saving mode and second time period of regulating mode. In the power-saving mode, the control circuit stops regulating the output of the power supply and turns off one or more functional blocks to allow the output to drop, until the output reaches a pre-set low output limit. In the regulating mode, the control circuit turns on the functional blocks and regulates the power supply to allow the output to increase, until the output reaches a pre-set high output limit.

Abstract: A Quasi-Resonant (QR) converter includes a power switch controlling the primary current flow and a time-varying capacitance coupled in parallel to the power switch. The time-varying capacitance is configured to add a frequency jitter to the frequency switch of the converter.

Abstract: A switch mode power supply (SMPS) system includes a rectifying circuit for coupling to an AC input voltage and a transformer having a primary winding for coupling to the rectifying circuit and a secondary winding coupled to the primary winding. The system also has a power switch coupled to the primary winding and a control circuit coupled to the power switch. The control circuit is configured to control current flow in the primary winding such that an envelope waveform formed by peak points of current pulses is in phase with the magnitude of the AC input voltage. Moreover, the SMPS system is configured to provide a constant average output current.

Abstract: A gate driver circuit includes an input terminal for receiving an input switching signal for driving a switching circuit that has a high-side transistor and a low-side transistor vertically stacked. The gate driver circuit also includes a dead-time control circuit, that includes two dead-time measurement circuits. The first dead-time measurement circuit produces a first pulse signal having a first pulse width representing a first dead-time between when a gate voltage of the low-side transistor falls below a first threshold voltage and when a gate voltage of the high-side transistor rises above a second threshold voltage. The second dead-time measurement circuit produces a second pulse signal having a second pulse width representing a second dead-time between when the gate voltage of the high-side transistor falls below the second threshold voltage and when the gate voltage of the low-side transistor rises above the second threshold voltage.