Patents Assigned to Display Technologies
  • Publication number: 20070046587
    Abstract: A precharge voltage Vp is applied in period A. The precharge voltage Vp is generated by applying a constant current Iw to a pixel driving transistor of a display panel and using gate terminal voltage of the driving transistor which passes the constant current Iw. The gate terminal potential is held in memory. When displaying images on a display panel, the gate terminal potential is read out of memory, and used as the precharge voltage Vp after arithmetic processing. By the application of the precharge voltage Vp, a source signal line is charged and discharged quickly so that an almost target tone current will flow through the driving transistor. Furthermore, a more accurate program current is written into the pixel during period B.
    Type: Application
    Filed: January 20, 2006
    Publication date: March 1, 2007
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Hiroshi Takahara
  • Patent number: 7182209
    Abstract: A glide (20) includes a base (22), a front member, and a number of walls (26) extending front-to-back. Both the base and the front member are advantageously formed as a number of pieces secured side-by-side to provide expandability. The front member may be secured to the walls via dovetail interaction and different front members may be provided for different wall spacings.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: February 27, 2007
    Assignee: Display Technologies, LLC
    Inventor: Anthony C. Squitieri
  • Patent number: 7184285
    Abstract: In order to restrict variations of an output voltage of a DC—DC conversion circuit using TFTs, in a boost-type, a second n-ch TFT N2 and a second p-ch TFT P2 are newly provided. With regard to the second n-ch TFT N2, a gate thereof is connected to a second capacitor C2, a source thereof is connected to a first reference voltage source YVDD, and a drain thereof is connected to a first capacitor C1. With regard to the second p-ch TFT P2, a gate thereof is connected to the second capacitor C2, a source thereof is connected to a third capacitor C3, and a drain thereof is connected to the first capacitor C1. Thus, a voltage at the first capacitor C1 stops being influenced by the variations of a threshold voltage between a source and drain of a first diode D1.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: February 27, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Masao Karube
  • Publication number: 20070040762
    Abstract: A planar display device includes: a first display panel having a plurality of first scan lines and a plurality of first signal lines; a second display panel having a plurality of second scan lines and a plurality of second signal lines; and a second selective connection circuit in which the plurality of second signal lines are categorized into a plurality of second signal line groups respectively representing different colors, with the plurality of second signal lines associated with the first signal lines in a first signal line group which are connected to a plurality of image signal supplying lines. In a case where a second display is performed by use of the second display panel, the second selective connection circuit connects all of the second signal lines to the corresponding first signal lines in the first signal line group.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 22, 2007
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Koji Shigehiro
  • Publication number: 20070040985
    Abstract: A polishing speed of large glass plate 51 subjected to a thermal treatment is slower than that of a large glass plate not subjected to such a thermal treatment when a chemical polishing process is applied to make those large glass plates thin. Large glass plate 51 prepared with a thermal history of a temperature of 400° C. is assembled with large glass plate 53 prepared with a thermal history of a temperature of not higher than 220° C. Large glass plates 51 and 53 are then immersed in chemical polishing solution and taken out therefrom simultaneously. Large glass plate 51 is made thinner in thickness than large glass plate 53. This causes great improvement in production yield of an LCD device.
    Type: Application
    Filed: May 23, 2006
    Publication date: February 22, 2007
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Yasushi KAWATA, Akio MURAYAMA
  • Patent number: 7180513
    Abstract: In a semiconductor circuit of a current output type, when display is performed by plural semiconductor circuit in one display panel, luminance unevenness for each block with a different semiconductor circuit occurs due to fluctuation in the semiconductor circuits. In current output stages, current mirror circuits are constituted at both ends of a chip, and a reference current to be a reference of gradation display is supplied from both the ends. Moreover, by increasing a resistance value of a gate line of the current mirror circuit of distributing a current to each output, deviation of a transistor threshold value in the chip was compensated for, and output currents at left and right ends were matched.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: February 20, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Hitoshi Tsuge
  • Publication number: 20070034859
    Abstract: An optical device comprising an anode, a cathode comprising barium, strontium or calcium, and a layer of organic semiconducting material between the anode and the cathode wherein a layer of hole transporting and electron blocking material is located between the anode and the layer of organic semiconducting material.
    Type: Application
    Filed: March 19, 2004
    Publication date: February 15, 2007
    Applicant: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED
    Inventors: Brian Tierney, Ilaria Grizzi, Clare Foden, Nalin Patel, Mark Leadbeater
  • Publication number: 20070034832
    Abstract: A polymer for use in an optical device comprising one or more regions, where each region comprises (i) a first structural unit having general formula I: where m=1 or 2 and which contains at least one substituent selected from the group consisting of alkyl, alkoxy, aryl, aryloxy, heteroaryl, and heteroaryloxy groups, each of which may be further substituted; and (ii) a second structural unit Ar selected from the group consisting of heteroaryl, triarylamine and 2,7-fluorenyl; such that where m=1 each region comprises a unit having general formula II: wherein, the substituent has a molecular weight of less than 300.
    Type: Application
    Filed: October 24, 2006
    Publication date: February 15, 2007
    Applicant: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED
    Inventors: Richard O'Dell, Carl Towns, Mary McKiernan
  • Publication number: 20070035502
    Abstract: A liquid crystal display device which enables a reduction in power consumption at low cost, includes: a liquid crystal display panel having signal lines and scan lines arranged in a matrix; a gate driver configured to supply a gate signal to any of the scan lines; a source driver having a shift register which outputs video data during a video display period, a second data storing section configured to store second data which are applied to each of the pixel electrodes and which are independent of the video data, and a D/A converting section configured to execute a D/A conversion on the data acquired from the shift register and the second data storing section and to supply a voltage to the signal line; and a timing control section configured to control a timing at which the video data from an input video signal is inputted to the shift register, a timing at which the D/A converting section acquires the video data from the shift register, and a timing at which the D/A converting section acquires the second data
    Type: Application
    Filed: August 9, 2006
    Publication date: February 15, 2007
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Seiji Kawaguchi
  • Publication number: 20070029940
    Abstract: In the present invention, only in screen display with a low lighting ratio in which low gradation display, which tends to cause writing insufficiency, is often performed, a writing current is multiplied by N to increase a characteristic fluctuation compensation ability of driving and transistors and reduce display unevenness. In addition, the number of frames to which an N-fold electric current is fed is reduced. Consequently, display with influences of an increase in electric power and a decline in a life controlled to a minimum limit is realized.
    Type: Application
    Filed: June 15, 2006
    Publication date: February 8, 2007
    Applicant: Toshiba Matsushita Display Technology Co., Ltd
    Inventor: Hitoshi Tsuge
  • Patent number: 7173103
    Abstract: A process for preparing high molecular weight polymers or copolymers by Suzuki coupling. The catalyst used in the process comprises a source of palladium and a source of a phosphine characterized in that at least one substituent on the phosphine is an ortho substituted aryl group. The process is suitable for the preparation of polymers for use in electronic and optoelectronic applications.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: February 6, 2007
    Assignee: Cambridge Display Technology Limited
    Inventors: Carl Towns, Paul Wallace, Ian Allen, Thomas Pounds, Lorraine Murtagh
  • Patent number: 7173681
    Abstract: In an electrode substrate used in a liquid crystal display device, a contact hole for connecting a signal line to a drain electrode of a pixel thin film transistor is provided in a position overlapping a pixel electrode in order to improve yields by reducing a short circuit between adjacent pixel electrodes. With this configuration, the contact hole does not exist at a boundary between the two adjacent pixel electrodes. Accordingly, the pixel electrodes do not suffer an influence of an electrode material remaining at a recess of the contact hole, and a short circuit between the adjacent pixel electrodes can be thereby prevented.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: February 6, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Hideyuki Takahashi, Kohei Nagayama, Mamoru Furuta, Shinichi Kawamura, Toshihiro Ninomiya, Koji Soma
  • Patent number: 7165875
    Abstract: The present invention prevents a defective display attributed to a non-uniform gap between a display element and a backlight which is caused by a phenomenon that an inner wall of a mold casing is shaved off by an end periphery of the display element and a shaved-off debris remains between the casing and the display element. Guide projections are integrally formed on an inner wall of a picture-frame-like portion of the mold casing and, at the same time, a gap which accommodates the shaved-off debris is formed between the guide projection and a bottom portion of the mold casing.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: January 23, 2007
    Assignees: Hitachi Displays, Ltd., Hitachi Display Technologies, Ltd.
    Inventors: Atsushi Ohtomo, Masahiro Katou
  • Publication number: 20070013822
    Abstract: Liquid crystal material 4 is held between first and second substrates 2 and 3 to form pixel portion 5 which include glass plates 10 and 11, respectively. The upper surface of first substrate 2 opposite to second substrate 3 includes a chip mounting portion on which IC chip 6 is mounted to drive liquid crystal material 4. The upper surface of IC chip 6 mounted on semiconductor chip mounting portion 20 and that of second substrate 3 are simultaneously lapped until the upper surface of IC chip 6 becomes the same in height and in plane as that of second substrate 3.
    Type: Application
    Filed: March 1, 2006
    Publication date: January 18, 2007
    Applicant: Toshiba Matsushita Display Technology Co., Ltd
    Inventors: Yasushi Kawata, Akio Murayama
  • Patent number: 7164164
    Abstract: A display device has display elements provided inside of pixels, each being formed in vicinity of intersections of signal lines and scanning lines aligned in matrix form; and photoelectric conversion elements, wherein each of the photoelectric conversion elements includes first, second and third semiconductor regions disposed adjacently in sequence in parallel to a surface of a substrate; a first electrode connected to the first semiconductor region; and a second electrode connected to the third semiconductor region, the first semiconductor region being formed by injecting a first conductive impurity in first dose amount; the third semiconductor region being formed by injecting a second conductive impurity in second dose amount; and the second semiconductor region being formed by injecting the first conductive impurity in third dose amount less than the first dose amount.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: January 16, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Takashi Nakamura, Norio Tada, Masahiro Tada
  • Patent number: 7161571
    Abstract: A programmable controller having three well-known components used in display controls but put under the control of a programmable ‘sub-field ’ timing generator is disclosed. The three well-known components include a Phase Lock Loop (PLL) unit, a Pixel Pipe Line (PPL) unit and an embedded frame buffer. Even though these are well known and understood components, each one is implemented to support the field and sub-field concepts of field sequential color (FSC) as well as non-FSC TFT display devices. The programmable controller also includes some new components that are unique to FSC displays. These new components include a color light sequencer to control the LED controls (or whatever color light source used) and programmable Source and Gate driver controls to accommodate the extremely wide diversification between different display panels.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: January 9, 2007
    Assignee: Hunet Display Technology Inc.
    Inventors: Robert M. Nally, Masaya Okita
  • Patent number: 7157157
    Abstract: There is provided an organic EL element including an anode, a cathode, and an organic layer, wherein the cathode includes a protective conductor layer which faces the organic layer, a main conductor layer which is interposed between the protective conductor layer and the organic layer, and a barrier layer which is interposed between the protective conductor layer and the main conductor layer and made of an insulator or a semiconductor.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: January 2, 2007
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Kazushige Yamamoto, Mikio Nakasuji
  • Publication number: 20060290611
    Abstract: [Problem to be Solved]To provide a current output type semiconductor circuit and a display device which are capable of realizing a reduction in cost by reducing the number of output stages and reducing a chip area. [Solution] A display device includes three reference current generating units 61 which generate reference currents corresponding to three display colors and outputs the reference currents, a selector 471 which outputs an optimum reference current among the outputs of the three reference current generating units 61 according to a display color of display data 473 in response to a changing display color switching signal 475, a current output unit 255 which outputs a current corresponding to a value of the display data 473 with respect to a current per one gradation determined by the reference currents, and a selector 472 for distributing the output of the current output unit 255 to respective source signal lines corresponding to the display color.
    Type: Application
    Filed: March 1, 2006
    Publication date: December 28, 2006
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Hitoshi Tsuge
  • Publication number: 20060285057
    Abstract: To suppress occurrence of low temperature bubbles while securing pressure resistance to external forces applied to substrates of a liquid crystal display device, a plurality of spacers disposed between the substrates are divided into a plurality of spacer groups 2, one unit of which is configured with spacers 2a, 2b allocated in close proximity to each other; and the spacer groups 2 are disposed with a density that the low temperature bubbles do not occur. Hence, the strength of the substrates increases, and in a region 10 where no spacers exist, a large deformation of the substrates by shrinkage is allowed, and a liquid crystal layer 8 is sufficiently enough shrunk even under a low temperature environment to prevent the low temperature bubbles from occurring.
    Type: Application
    Filed: May 17, 2006
    Publication date: December 21, 2006
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Tetsuya Kawamura, Katsuhiko Inada, Akimasa Toyama
  • Publication number: 20060284826
    Abstract: The liquid crystal display device includes an active matrix type liquid crystal display panel using OCB mode liquid crystal, a source/gate driving unit, a backlight and a backlight control unit which controls the backlight to turn on/off periodically, the backlight control unit periodically assigns on and off periods of the backlight, the ON/OFF period of the backlight is controlled such that the relationship between the assigned ON/OFF period TB of the backlight and a switching period TG of a gate line in the liquid crystal display panel is given by TB=(1/n)·TG (n: natural number)
    Type: Application
    Filed: May 26, 2006
    Publication date: December 21, 2006
    Applicant: Toshiba Matsushita Display Technology Co., Ltd
    Inventor: Seiji Kawaguchi