Abstract: A manufacturing method of a double LDD MOS transistor includes forming a gate electrode on a semiconductor substrate; forming a first LDD area by implanting and thermally annealing impurity ions using the gate electrode as a mask; forming a first spacer on both lateral walls of the gate electrode; forming a second LDD area by implanting and thermally annealing impurity ions using the gate electrode and the first spacer as a mask; forming a second spacer on both lateral walls of the gate electrode and the first spacer; and forming a source-drain diffusion area by implanting and thermally annealing impurity ions using the gate electrode, the first spacer, and the second spacer as a mask.

Abstract: A fabricating method of a CMOS image sensor is disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The CMOS image sensor includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes, an insulating interlayer on a plurality of the inner microlenses, a plurality of metal lines within the insulating interlayer, a device protecting layer on the insulating interlayer, and a plurality of microlenses on the device protecting layer.

Abstract: Provided is an image sensor including an overcoating layer and at least two micro lenses formed on the overcoating layer. The image sensor is characterized in that the overcoating layer positioned below a clearance between the micro lenses is etched such that curved surfaces of the micro lenses extend to the etched overcoating layer, and a contamination in the bonding pad can be prevented.

Abstract: Disclosed is a method of measuring a pattern shift in a semiconductor device. The method measures a mobility or shift distance of a stepped portion occurring between a buried layer surface and a substrate surface during an epitaxial process on the buried layer. The method includes the steps of: recognizing a first width ratio of a metallic wiring over a stepped pattern in an insulation film shifted by a certain distance and measuring a first capacitance value of a capacitor including the metallic wiring, forming a first pattern having a second width ratio different from the first width ratio, measuring a capacitance value of the first pattern, forming multiple patterns having width ratios different from the first and second width ratios, measuring capacitance values of the multiple patterns, establishing reference values using the measured capacitance values, and comparing the first capacitance value with any one of the established reference values to recognize a shift distance of the stepped pattern.

Abstract: Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.

Abstract: A CMOS image sensor and a method for fabricating the same prevent a lifting effect of microlenses. Also, a diffused reflection of microlenses is prevented. The CMOS image sensor includes photodiodes, an interlayer insulating layer, metal lines formed in the interlayer insulating layer to electrically connect the respective photodiodes with each other, an oxide layer, a passivation layer to protect the CMOS image sensor from external sources, and microlenses formed to pass through the passivation layer at portions corresponding to the photodiodes.

Abstract: A method for forming a plug of a semiconductor device according to a preferred embodiment includes forming a metal wiring on a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate having the metal wiring, forming a contact hole for partially exposing the metal wiring by selectively etching the interlayer dielectric layer, annealing the semiconductor substrate having the contact hole using NH3 gas, plasma processing the annealed semiconductor substrate using the NH3, and forming a barrier layer on the interlayer dielectric layer having the contact hole.

Abstract: A method for forming a mask pattern of a semiconductor device is disclosed. An example method arranges a main pattern and arranges a first fine auxiliary pattern in the vicinity of the main pattern. The example method also arranges a second fine auxiliary pattern in the vicinity of edges of the main pattern. In the example method, the second fine auxiliary pattern has a predetermined tilt angle with respect to the first fine auxiliary pattern.

Abstract: Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting ions into opposite sides of the gate pattern, to form a lightly doped drain structure while implanting ions into a portion of the high-voltage device region under the same conditions as the low-voltage device region to form an electrostatic discharge protecting device region; forming a spacer at the side surface of the gate pattern; forming a source region and a drain source at field regions disposed at the opposite sides of the gate pattern, respectively; and forming a metal layer on the front surface of the substrate including the gate pattern.

Abstract: A CMOS image sensor and a method for manufacturing the same improves photosensitivity and prevent loss of light by forming a photo-sensing unit under a color filter. The CMOS image sensor may include a plurality of transistors formed on a semiconductor substrate, a metal line formed over the plurality of transistors for electrically connecting the plurality of transistors, and a plurality of photodiodes electrically connected with the plurality of transistors and formed over the metal line.

Abstract: A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity in the first well to form a third well; forming and patterning a conductive layer on the third well region to form a base electrode pattern; forming a spacer on a sidewalls of the base electrode pattern; implanting first conductivity type ions in the semiconductor substrate to form an emitter region adjacent to the base electrode pattern and form a collector region in the second well region; and performing a diffusion process to form a base region adjacent to the emitter region.

Abstract: An exemplary manufacturing method of an inter-metal dielectric of a semiconductor device according to an embodiment of the present invention includes forming a first silicon-rich oxide (SRO) layer on a silicon substrate provided with or otherwise having a copper line layer therein, forming a plasma enhanced fluorosilicate glass (PEFSG) layer on the first SRO layer, plasma-treating the PEFSG layer, and forming a second SRO layer on the plasma-treated PEFSG layer. According to the present invention, the thickness of the second SRO layer of the inter-metal dielectric can be reduced. Consequently, process cost can be reduced, and the total thickness of the inter-metal dielectric can be reduced so as to lower the dielectric constant thereof, reduce the aspect ratio of any via holes that are subsequently formed in the inter-metal dielectric, and potentially increase the yield as a result of the reduced via hole aspect ratio.

Abstract: A CMOS image sensor and a method for manufacturing the same improve light-receiving efficiency and maintain a margin in the design of a metal line. The CMOS image sensor includes a transparent substrate including an active area having a photodiode region and a transistor region and a field area for isolation of the active area, a p-type semiconductor layer on the transparent substrate, a photodiode in the p-type semiconductor layer corresponding to the photodiodes region, and a plurality of transistors in the p-type semiconductor layer corresponding to the transistor region.

Abstract: A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed.

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating layer on a semiconductor substrate having a semiconductor chip region and a scribe region; forming a mask pattern on the first insulating layer; removing portions of the first insulating layer using the mask pattern so as to form a contact hole in the semiconductor chip region and a scribe region opening exposing the scribe region; forming a metal contact plug in a contact hole and a metal sidewall on a side of the first insulating layer in the scribe region opening; forming a metallization wiring on the first insulating layer; and forming a second insulating layer and a protective layer over the metal contact plug and the metal sidewall so as to cover the semiconductor chip region and the scribe region.

Abstract: A CMOS image sensor includes a substrate including a sensing part and a peripheral driving part; a first insulating interlayer formed over an entire surface of the substrate; a first metal line formed on the first insulating interlayer in each of the sensing and peripheral driving parts; a second insulating interlayer formed over the entire surface of the substrate including the first metal line; a second metal line formed on the second insulating interlayer in each of the sensor and peripheral drive parts; an etch-stop layer formed over the entire surface of the substrate including the second metal line; a third insulating interlayer formed on the peripheral driving part of the etch-stop layer; a third metal line formed on the third insulating interlayer; a fourth insulating interlayer formed on the third insulating interlayer including the third metal line, to be disposed in the peripheral driving part; and a fourth metal line formed on the fourth insulating interlayer.

Abstract: A semiconductor and a method of fabricating the same are provided. The method includes: forming an insulation layer on a substrate; forming a trench by selectively etching the insulation layer; electroplating a copper layer in the trench and on the insulation layer under such conditions that a seam is formed at a top middle portion of the trench; and polishing the copper layer to form a copper metal line with the seam.

Abstract: A method of fabricating a semiconductor device having a capacitor is provided. The method includes forming second, third, fourth, and fifth insulating layers on a first conductive layer formed in a first insulating layer. The fourth insulating layer is patterned into a first pattern before forming the fifth insulating layer thereupon. A capacitor and contact plug are formed by etching the fifth insulating layer to expose the first pattern; etching the third insulating layer using the exposed first pattern as a mask to expose the second insulating layer; exposing the first conductive layer at a capacitor region and contact plug region by etching the exposed second insulating layer; forming a second conductive layer on the exposed first conductive layer and sidewalls of the insulating layers; forming a dielectric on the second conductive layer in the capacitor region; and filling the capacitor and contact plug regions with a third conductive layer.

Abstract: A method for forming a thin film of a semiconductor device is provided. The method includes forming a TaN film on a semiconductor substrate, and converting a portion of the TaN film into a Ta film by reacting the TaN film with NO2. The Ta film is formed to have a thickness which is about half of the thickness of the TaN film.

Abstract: Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region.