Abstract: A method for manufacturing an image sensor is provided. The method includes: forming a plurality of photodiodes on a semiconductor substrate; forming an interlayer dielectric on the semiconductor substrate; forming a color filter layer on the interlayer dielectric; forming a planarization layer on the color filter layer; and forming microlenses on the planarization layer under high temperature and pressure.

Abstract: Disclosed are a CMOS image sensor capable of improving the focusing capability of light and a method for manufacturing the same. The CMOS image sensor includes a plurality of first micro-lenses formed in the upper part of the planarization layer, each of the first micro-lenses arranged over a corresponding photodiode, and a plurality of second micro-lenses formed on the planarization layer, each of the plurality of second micro-lenses wrapping a corresponding first micro-lens respectively.

Abstract: A CMOS image sensor and a manufacturing method thereof are disclosed. The gates of the transistors are formed in an active region of a unit pixel, and at the same time, a passivation layer is formed on an edge portion of the active region of a photodiode to have the same laminate structure as the gates of the transistors. Impurities for a diffusion region of the photodiode are ion-implanted into the active region for the photodiode, after the laminate structure is formed. The passivation layer prevents the edge portion from being damaged by ion implantation at the boundary or interface between the photodiode diffusion region and an isolation layer, which reduces dark current and/or leakage current of the CMOS image sensor.

Abstract: A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern layer over a flash memory channel region of a semiconductor substrate; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer as a mask; removing portions of the sacrificial insulating pattern layer; sequentially forming an ONO-type dielectric layer and a gate material layer; selectively etching the gate material layer and at least part of the gate dielectric layer to form a gate; and forming gate sidewall spacers at sides of the gate.

Abstract: Disclosed is a system and method for automatically measuring carrier density distribution by using capacitance-voltage characteristics of a MOS transistor device. System comprises an automatic probe station for measurement of an object wafer, the automatic probe station being electrically connected to the wafer; a capacitor measuring unit having a high frequency terminal and a low frequency terminal; and a control computer for being respectively connected the automatic probe station and the capacitor measuring unit, wherein the high frequency terminal is connected to a gate of the wafer and the low frequency terminal is connected to a substrate of the wafer.

Abstract: A method of manufacturing a split gate type non-volatile memory device includes the steps of defining an active region on a semiconductor substrate; forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the substrate and the first conductive film pattern, on the active region; forming a second conductive film on top of the first conductive film patterns and a remainder of the active region; etchbacking the entire surface of the second conductive film to planarize a top of the second conductive film formed between the first conductive film patterns; forming a photoresist pattern, with an opening corresponding to the active region between the first conductive film patterns, on the second conductive film; and forming a pair of split gates each having one of the first conductive film patterns and a second conductive film pattern formed by patterning the second conductive film using the photoresist pattern as an etching mask.

Abstract: Disclosed is a well photoresist pattern of a semiconductor, and the fabrication method thereof. The method includes the steps of: (a) forming a sacrificial oxide layer on a semiconductor substrate; (b) applying a primer on the sacrificial oxide layer; (c) applying a photoresist on the primer; (d) soft-baking the photoresist; (e) exposing the photoresist to light by defocusing the DOF (depth of focus) of the light transmitted to the substrate; (f) post exposure baking the photoresist; (g) developing the photo-exposed photoresist to form a well photoresist pattern; and (h) hard-baking the well photoresist pattern. It is preferable that the exposure is performed by plus(+) defocusing of light.

Abstract: A CIS and a method for manufacturing the same are provided. The CIS includes an interlayer insulation layer formed on a substrate having a photodiode and a transistor formed thereon; a plurality of color filters formed on the interlayer insulation layer and spaced a predetermined interval apart from each other; a metal sidewall formed to fill the predetermined interval between the plurality of the color filters; and a microlens formed on each of the plurality of color filters.

Abstract: Disclosed is a method for fabricating an Al metal line. The method includes forming an insulating layer on a semiconductor substrate; forming a Ti layer, a bottom TiN layer, an Al layer and a top TiN layer in successive order on the insulating layer; plasma-treating the top TiN layer; forming a photoresist pattern on the plasma-treated top TiN layer; and etching the plasma-treated top TiN layer, the Al layer, the bottom TiN layer, and the Ti layer using the photoresist pattern as an etching mask, thereby forming the Al metal line.

Abstract: A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of group IIIA element atom layers may comprise Al, Ga, In, and/or Tl.

Abstract: Methods of forming a metal line in a semiconductor device. A method includes: depositing a first etch stop layer, an interlayer insulating layer, a second etch stop layer, and a line insulating layer on a semiconductor substrate; forming a contact hole pattern on the line insulating layer; forming a contact hole by etching an exposed portion of the interlayer insulating layer using the contact hole pattern as a mask; forming a trench pattern on the line insulating layer; forming a trench by etching an exposed portion of the line insulating layer using the trench pattern as a mask; removing exposed portions of the first etch stop layer and the second etch stop layer after forming the contact hole and the trench; forming a first metal thin film within the contact hole; and forming a second metal thin film on the first metal thin film.

Abstract: A method of fabricating a floating gate of a flash memory device is provided. The method includes: forming a tunneling oxide layer on a substrate; forming a conductive thin layer on the tunneling oxide layer; applying a photoresist on the conductive thin layer; defining a floating gate region by patterning the photoresist; forming polymer sidewalls on the sides of the patterned photoresist; and selectively removing the conductive thin layer using the photoresist and the polymer sidewalls as a mask to form a floating gate.

Abstract: A method of manufacturing a semiconductor device including forming a trench on a first surface of a silicon substrate, forming a thermal oxide layer and a deposited oxide layer on the trench and the silicon substrate, planarizing a second surface of the silicon substrate by a chemical mechanical polishing (CMP) process, and forming a transistor on the second surface of the silicon substrate. The semiconductor device and the method of manufacturing the same provide an SOI device that has low resistance of the source/drain regions and suppress a short channel effect.

Abstract: A tungsten plug structure of a semiconductor device wherein a method for forming the same is performed at least twice to form a tungsten plug having a low aspect ratio, thereby obtaining an overlap margin between the tungsten plug and a metal line and minimizing contact resistance between the tungsten plug and a lower metal line layer. The plug structure of a semiconductor device includes a silicon substrate in which various elements for the semiconductor device are formed, a first dielectric film formed on the silicon substrate, having a first contact hole, a first plug buried in the first contact hole of the first dielectric film, having a low aspect ratio, a second dielectric film formed on an entire surface including the first dielectric film, having a second contact hole on the first plug, a second plug buried in the second contact hole of the second dielectric film, having a low aspect ratio, and a metal line formed on the second plug.

Abstract: A semiconductor device and method of manufacturing same, capable of preventing the material of a barrier metal layer from penetrating into an intermetallic insulating layer are provided. In an embodiment, the device can include: a first metal interconnection formed in a lower insulating layer on a semiconductor substrate; an intermetallic insulating layer formed on the lower insulating layer including the first metal interconnection, the intermetallic insulating layer having a via hole and a trench for a second metal interconnection connecting to the first metal interconnection; a carbon implantation layer formed on inner walls of the via hole and the trench of the intermetallic insulating layer; a barrier metal layer deposited on the first metal interconnection exposed through the via hole and on the carbon implantation layer; a via formed in the via hole; and the second metal interconnection formed in the trench.

Abstract: Provided is a semiconductor device capable of reducing the resistance of the gate electrode of a transistor. The semiconductor device comprises a semiconductor substrate, a gate oxide film formed on the substrate, a gate formed on the gate oxide film, and a metal silicide layer formed on the top surface and the upper side surface of the gate.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device is provided. The method includes simultaneously patterning a lower metal film pattern and a dielectric film pattern to form a first structure in a MIM capacitor region and a second structure in a metal line region, removing the dielectric film pattern in the metal line region, forming a second insulating film to cover the dielectric film pattern in the MIM capacitor region and the lower metal line film pattern in the metal line region, simultaneously forming a trench that exposes the dielectric film pattern in the MIM capacitor region and a via hole that exposes the lower metal line film pattern in the metal line region by passing through the second insulating film, and forming an upper metal electrode film pattern and a via contact to respectively bury the trench and the via hole.

Abstract: A method for manufacturing a semiconductor device includes steps of injecting a hole current into an N drift region while a constant voltage is applied to a P+ anode of a lateral insulated gate bipolar transistor, such that a majority of the hole current passes through a P+ cathode of the lateral insulated gate bipolar transistor via a P+ buried layer. Therefore, a hole-current path located under an N+ cathode area of a LIGBT structure is eliminated, thus securing sufficient latch-up current density.

Abstract: A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.

Abstract: An exemplary method of forming a contact hole in a semiconductor device includes: forming a first insulation layer on a lower substrate; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first insulation layer and the first conductive layer; forming a second conductive layer on the second insulation layer; forming a third insulation layer on the second insulation layer and the second conductive layer; patterning a resist on the third insulation layer using an exposure mask of which transmittance is different at a region over the first conductive layer and at a region over the second conductive layer; and forming a first contact hole and a second contact hole by etching the resist and the third insulation layer such that the first conductive layer and the second conductive layer are exposed.