Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole's upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.

Abstract: A method for forming a metallization contact in a semiconductor device includes (a) forming an insulating layer on a semiconductor substrate including an active device region or a lower metal wire; (b) forming a contact hole to expose a portion of the active device region or lower metal wire by etching a portion of the insulating layer; (c) depositing a first TiN layer on the insulating layer and inside the contact hole by a PVD process using a first carrier gas composition of nitrogen (N2) and argon (Ar); (d) depositing a second TiN layer on the first TiN layer by a PVD process using a second carrier gas composition of nitrogen (N2) and argon (Ar); and (e) forming a metal layer on the second TiN layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the steps of forming a gate oxide layer including an oxide layer containing a large amount of nitrogen on a semiconductor substrate on which an input/output (I/O) region including an NMOS region and a PMOS region are defined, forming a polysilicon on the gate oxide layer, selectively removing the polysilicon on the PMOS region, selectively removing the gate oxide layer on the PMOS region, forming a pure SiO2 layer on the semiconductor substrate of the PMOS region, removing a surface oxide layer on the remaining polysilicon generated when the pure SiO2 layer is formed, and forming a gate electrode polysilicon on the entire surface including the remaining polysilicon.

Abstract: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on the exposed portion of the substrate, removing the patterned first insulation layer, and forming transistors on the substrate and epitaxial layer, respectively. The epitaxial layer is grown to a degree that an upper surface of the epitaxial layer is higher than that of the substrate.

Abstract: A bipolar transistor and method of fabricating the same is disclosed. Particularly, a bipolar transistor may have an emitter and a collector diffusion layer in the sidewalls and the bottom of a device isolation trench. A method includes the steps of: forming a device isolation trench in a substrate; forming a photoresist pattern and implanting ions into the sidewalls and the bottom of the trench to form an emitter and a collector; removing the photoresist pattern; and filling the trench with an insulation layer to form the device isolation structure. Accordingly, the transistor and method can minimize device area by forming the diffusion layer of an emitter and a collector in the sidewalls and the bottom of the trench, and can provide a deep impurity diffusion layer without a high temperature diffusion process. In addition, the transistor and method can provide both a high amplification factor and a high current driving force.

Abstract: A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions.

Abstract: A capacitor capable of being formed in a vertical plane without an additional mask process and/or deposition process and a method of manufacturing the same are provided. The capacitor includes: a first conductive line formed on a substrate; a first interlayer dielectric including a first via hole formed at an upper portion of the first conductive line, and a second and third via hole pair formed at a region of the substrate; a first barrier metal layer and a contact plug formed in the first via hole; and first and second capacitor electrodes formed in the second and third via holes, respectively. The first and second capacitor electrodes and the first interlayer dielectric disposed between the first and second capacitor electrodes form a vertically constructed capacitor.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of th

Abstract: A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.

Abstract: A method for manufacturing a semiconductor device, includes sequentially forming a first insulation film and a dummy gate electrode on a semiconductor substrate; forming a lightly doped junction region by using the dummy gate electrode as a mask, forming a first spacer on a side wall of the dummy gate electrode, and then forming a heavily doped junction region. The method further includes forming a second insulation film on the semiconductor substrate where the heavily doped junction region is formed, and removing the dummy gate electrode to form a cavity exposing a portion of the first insulation layer; forming a second spacer on a side wall of the cavity; sequentially forming a gate insulation film and a gate conductor on the second spacer, and then removing the second insulation film and a portion of the gate insulation film; and forming a salicide film on a top of the gate conductor and in the lightly doped junction region.

Abstract: A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad oxide film and the nitride film; forming a trench in the exposed semiconductor substrate; forming a gap-fill dielectric film in the trench; exposing an active area of the semiconductor substrate by removing the pad oxide film and the nitride film; forming an epitaxial layer including a dopant in the exposed active area; forming a gate electrode on the epitaxial layer; and forming source and drain regions in the active area beside the gate electrode. The semiconductor device can prevent surface damage of a semiconductor substrate, may occur when performing ion implantation for threshold voltage control, and does not require annealing after ion implantation.

Abstract: Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being destroyed due to electro-migration (EM) and stress-migration (SM). An illustrated metal interconnection line includes: a semiconductor substrate; a metal pattern on the substrate; a glue pattern under the metal pattern; an anti-reflection pattern on the metal pattern; and dummy patterns surrounding side walls of the metal pattern.

Abstract: Electrical characteristics of a semiconductor device may be enhanced by completely removing a residue such as a polymer formed in a trench when the semiconductor device is manufactured by a method including: forming a via hole and a trench on a semiconductor substrate by an etching process; coating a photoresist on an entire surface of the semiconductor substrate such that the via hole and the trench may be filled thereby; removing a polymer defect in the trench while removing the coated photoresist by a plasma treatment under predetermined process conditions; and performing a wet cleaning process so as to remove a residue of the photoresist.

Abstract: Nonvolatile memory devices and methods of fabricating and driving the same are disclosed. Disclosed devices and method comprises: growing an oxide layer on a substrate and depositing a nitride layer on the oxide layer; patterning the nitride layer; forming injection gates on the lateral faces of the nitride layer; depositing a first polysilicon, a dielectric layer and a second polysilicon on the surface of the resulting structure, sequentially; patterning the second polysilicon, the dielectric layer and the second polysilicon to form gate electrodes; removing the nitride layer between the injection gates; forming source and drain extension regions around each of the gate electrodes by performing an ion implantation process; forming sidewall spacers on the lateral faces of the gate electrodes; and forming source and drain regions in the substrate by performing an ion implantation process with the sidewall spacers as an ion implantation mask.

Abstract: Disclosed are a CMOS image sensor and a method for manufacturing the same, capable of improving the characteristics of the image sensor by increasing junction capacitance of a floating diffusion area. The CMOS image sensor generally includes a photodiode and a plurality of transistors (e.g., transfer, reset, drive, and select transistors), a first conductive type semiconductor substrate, having an active area including a photodiode area, a floating diffusion area, and a voltage input/output area, a gate electrode of each transistor on the active area, a first conductive type first well area in the semiconductor substrate corresponding to the voltage input/output area, a first conductive type second well area in the semiconductor substrate corresponding to the floating diffusion area, and a second conductive type diffusion area in the semiconductor substrate at opposed sides of each gate electrode.

Abstract: Image sensors and methods of manufacturing an image sensor are disclosed. A disclosed photo diode may receive short wavelength light in its depletion region without exhibiting defective phenomenon such as noise and dark current. In the illustrated example, this performance is achieved by forming a trench type light-transmission layer to occupy a major surface of the photo diode so as to reduce the area available for defects on the surface of the semiconductor substrate. As a result of this reduction, the depletion region formed upon the operation of the sensor may extend toward the surface of the semiconductor substrate without concerned for defects. The image sensor may be manufactured without forming a blocking layer in connection with a silicide layer.

Abstract: The present invention relates to an image sensor chip package and a method for fabricating the same. In one embodiment of an image sensor chip package, chip pads on a first surface of an image sensor chip are attached to electrode pads of a glass substrate with conductive material. In addition, electrode pads are connected to solder balls via a metal wiring pattern arranged on a second surface of the image sensor chip. As a result, the present invention can provide further miniaturized and thinned image sensor chip packages, reduce fabricating processes, and improve device performance and reliability.

Abstract: A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.

Abstract: A method for manufacturing a thin film transistor includes forming a gate oxide film on a substrate, forming a first nitride layer on the gate oxide film, forming a polysilicon layer on the first nitride layer, forming a second nitride layer on sidewalls of the gate oxide film, first nitride layer, and polysilicon layer, and implanting impurity ions to form a pocket below the second nitride layer.

Abstract: A method of fabricating a CMOS image sensor is provided.