Abstract: A method of manufacturing a semiconductor device including forming a pad oxide layer on a semiconductor substrate, forming a spacer oxide layer pattern on sidewalls of the pad oxide layer, and forming a nitride layer on the pad oxide layer. The method further includes forming a groove in the nitride layer by selectively removing the spacer oxide layer pattern, forming a trench in a region where the groove is formed, and filling the trench with a thermal oxide layer so as to form a shallow trench isolation (STI) layer. In the method, the line width of the STI layer depends on the thickness of the spacer oxide layer, and so the STI layer can be formed to a line width W smaller than a design rule.

Abstract: An exemplary method of forming a shallow trench isolation layer in a semiconductor device according to an embodiment of the present invention includes depositing a silicon nitride layer as a hard mask layer on a silicon substrate, forming a first moat pattern in the silicon nitride layer by a photolithography process, patterning the silicon nitride layer by a dry etching process using the first moat pattern as an etching mask, forming a shallow trench by dry-etching the substrate that is exposed by the patterned silicon nitride layer, removing the first moat pattern after forming the shallow trench, removing the patterned silicon nitride layer, filling the shallow trench with a gap-fill insulation layer, forming a second moat pattern, removing the gap-fill insulation layer by a dry etching process using the second moat pattern as an etching mask, and removing the second moat pattern.

Abstract: A method of manufacturing a semiconductor device including forming a trench on a first surface of a silicon substrate, forming a thermal oxide layer and a deposited oxide layer on the trench and the silicon substrate, planarizing a second surface of the silicon substrate by a chemical mechanical polishing (CMP) process, and forming a transistor on the second surface of the silicon substrate. The semiconductor device and the method of manufacturing the same provide an SOI device that has low resistance of the source/drain regions and suppress a short channel effect.

Abstract: The present invention provides a non-volatile memory device and a method of manufacturing the same. The non-volatile memory device includes: a semiconductor substrate including an active region defined by an isolation layer, having a first conductivity type; a gate formed on the substrate; a first threshold voltage adjusting layer formed on a surface of an active region below the gate, having a second conductivity type; a second threshold voltage adjusting layer formed on a surface of an edge region of the isolation layer, having the first conductivity type; and an insulation layer formed between the gate and the substrate.

Abstract: A nonvolatile memory device including a floating gate formed on a tunnel oxide layer that is formed on a semiconductor substrate. The device also includes a drain region formed in the substrate adjacent to one side of the floating gate, a source region formed in the substrate adjacent to another side of the floating gate, where the source region is apart from the floating gate, and an inter-gate insulating layer formed on a portion of an active region between the source region and the floating gate and on a sidewall of the floating gate directing toward the source region, as well as on a sidewall of the floating gate directing toward the drain region. The device includes a word line formed over the floating gate and being across the substrate in one direction, and a field oxide layer interposing between the word line and the source region and between the word line and the drain region, and intersecting the word line.

Abstract: A method including forming a first mask material layer on a semiconductor substrate in order to mask a cell region and to not mask a peripheral circuit region. The method further includes forming a second mask material layer on an entire surface of the substrate in the cell region and peripheral circuit region, simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region, where the second depth is greater than the first depth. The method also includes filling an insulation layer into an entire surface of the substrate including trenches, planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed, and respectively forming an STI isolation layer in both the cell region and the peripheral circuit region by removing the first and second mask material layer.

Abstract: The present invention provides a flash memory device and a method of forming the same. The method includes: forming an isolation layer and a plurality of gate lines on a semiconductor substrate; forming a source/drain region by ion-implanting impurities into the semiconductor substrate using the gate lines as a mask; forming a side oxide layer on sidewalls and surfaces of the gate lines; forming a side nitride layer on the side oxide layer; forming an insulation layer on the semiconductor substrate and the side nitride layer; forming a photosensitive layer pattern on the insulation layer; exposing the source region between the gate lines by etching the insulation layer using the photosensitive layer pattern as a mask; forming a polysilicon layer on the exposed source region and the insulation layer; and forming a source line by etching the polysilicon layer.

Abstract: A method for fabricating a nonvolatile memory device including successively forming a first oxide layer, an electrically conductive layer, a second oxide layer, a nitride layer and a third oxide layer on a semiconductor substrate. The method also includes patterning the third oxide layer, forming spacers at sidewalls of the third oxide layer, forming a trench in the substrate by selectively etching the substrate with the third oxide layer as a mask, filling the trench with fourth oxide layer, and removing the third oxide layer, the nitride layer and the second oxide layer. Before filling the trench with the fourth oxide layer, a liner oxide layer is formed on inner walls of the trench. The fourth oxide layer is high density plasma (HDP) oxide and tetrafluoroethane (Si(OC2H5)4). During the filling the trench, lower corners of the conductive layer are made have rounded structure or bird's beak structure.

Abstract: A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and the silicon substrate to form a trench having a predetermined depth in the silicon substrate, and depositing a trench filling oxide to fill the trench. The method further includes polishing the trench filling oxide until the pad nitride is exposed, depositing a protective nitride to cover surface of the substrate including the pad nitride and the trench filling oxide, and isotropically etching the protective nitride and the pad nitride to form spacers.

Abstract: A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region and the isolation layer, and a sidewall spacer is formed at sidewalls of the gate stack. The device further includes a common source line that electrically interconnects a plurality of sources of a plurality of the flash memory cells, and is formed in the isolation layer by removing an insulating material in the isolation layer and is formed in parallel to a word line formed over the gate stack. A silicide layer is formed in the common source line.

Abstract: A MOS transistor having an extended drain structure and including a semiconductor substrate formed in a well of a first conductivity type. A gate insulating layer is formed on the substrate, a gate electrode is formed on the gate insulating layer, and a source region is formed in a first portion of the substrate, which is near to one side of the gate insulating layer and the gate electrode. A drain region is formed in a second portion of the substrate, which is near to another side of the gate insulating layer and the gate electrode. The second portion is recessed from the surface of the substrate by a predetermined depth.

Abstract: A flash memory device that has a structure capable of preventing gate stack damage, and a method of manufacturing the same, is presented. The method includes forming a first photo resist pattern to open a common source region on a substrate where a shallow trench isolation region, a tunnel oxide layer, and a gate stack including a floating gate, a dielectric layer and a control gate are formed, removing an insulating layer in the shallow trench isolation region with using the first photo resist pattern as a mask, and removing the first photo resist pattern. The method further includes depositing a buffer oxide layer on surface of the substrate to cover the gate stack and the common source region, forming a second photo resist pattern on surface of the substrate including the buffer oxide layer to open the common source region, and injecting dopants to the common source region by using the second photo resist pattern as a mask.

Abstract: A method fabricating multiple wiring metals in a semiconductor device. The method includes forming a lower wiring metal on a semiconductor substrate, forming an interlayer dielectric on the lower wiring metal, and selectively removing the interlayer dielectric to form a contact dielectric film, a body dielectric film and an opening between the contact and body dielectric films. The method also includes filling the opening with low-k material, forming a capping dielectric on the contact and body dielectric films and the low-k material, forming a contact hole passing through the capping dielectric and the contact dielectric film to be connected to the lower wiring metal, and forming an upper wiring metal electrically interconnected to the lower wiring metal through the contact hole.

Abstract: A nonvolatile memory device has a floating gate with its top and side surfaces covered by ONO film to improve the data retention of the floating gate. The ONO film has upper and lower silicon dioxide layers interposed by silicon nitride layer thinner than the oxide layers. A method includes the steps of forming a tunnel oxide layer on a silicon substrate, depositing a first polysilicon film on the tunnel oxide layer, patterning the first polysilicon film to form a floating gate, depositing oxide-nitride-oxide (ONO) film on the substrate surface to cover top and side surfaces of the floating gate, depositing a second polysilicon film on the ONO film, patterning the second polysilicon film to form a control gate, and selectively etching the ONO film to form an interlayer dielectric layer interposing between the floating and control gates and a sidewall spacer dielectric layer on sidewalls of the floating gate.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: A method for forming a metal interconnect of a semiconductor device defined by a fine trench or via is disclosed. The method includes forming a first interconnect insulating layer on a substrate. A via hole is formed on a predetermined portion of the first interconnect insulating layer. A second interconnect insulating layer is formed on the first interconnect insulating layer. The second interconnect insulating layer is planarized. A hard mask layer is formed on the second interconnect insulating layer. The hard mask layer is patterned to remove selective portions. A trench is formed by etching the second interconnect insulating layer. A metal interconnect is formed in the trench.

Abstract: In a double side stack packaging a plurality of chips, a hole is formed in a substrate. A first chip is attached to a bottom surface of the substrate by using a thermo compression and is electrically interconnected to terminals formed at sidewall of the hole using a wire bonding. Next, an epoxy is coated on the substrate and the first chip and a first heat spreader is installed thereon and then the epoxy is cured. Thereafter, a second chip is attached to a top surface of the substrate by using the epoxy and is electrically interconnected to terminals formed on the substrate using the wire bonding. And then, an encapsulation resin is coated on the substrate and the first chip and a second heat spreader is installed thereon and then the epoxy is cured.

Abstract: A semiconductor device and a method for fabricating the same. The device comprises a silicon substrate having a conductive well; a trench formed in the conductive well; a plate electrode formed on the sidewall of the trench; a capacitor insulating film and a storage node electrode; a first storage node connector formed on the storage node electrode; an insulating film formed on the first storage node connector; a silicon layer formed on the entire structure; word lines formed on the silicon layer; source and drain regions formed in the silicon layer; a contact hole, formed in the silicon layer and the insulating film, such that the first storage node connector and the source region are exposed; and a second storage node connector, formed in the contact hole, such that the source region and the first storage node connector are connected to each other.

Abstract: A semiconductor device and a method for manufacturing the same are provided. A gate insulating film is formed under a vacuum condition to prevent deterioration of reliability of the device due to degradation of a gate insulating material and to have stable operating characteristics. The semiconductor device includes an element isolating film formed at element isolating regions of a semiconductor substrate, which is divided into active regions and the element isolating regions; a gate insulating film having openings with a designated width formed at the active regions of the semiconductor substrate; gate electrodes formed on the gate insulating film; and lightly doped drain regions and source/drain impurity regions formed in the surface of the semiconductor substrate at both sides of the gate electrodes.

Abstract: A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.