Abstract: In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active area defined in a bit line direction and a word line direction, a plurality of floating gates formed in the word line direction, an interlayer polysilicon oxide film formed on a floating gate, a control gate formed on the interlayer polysilicon oxide film, source and drain electrodes disposed between adjacent floating gates in the word line direction, a buried N+ region formed in the semiconductor substrate under the source and drain electrodes, and a metal silicide film formed on an upper surface of the control gate.

Abstract: A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area, and a field oxide in the substrate for electrical isolation within the image area.

Abstract: A chain resistance pattern and a method of forming the same enable a test pattern to obtain maximum measurement results using minimum area and enable accurate detection of process errors. The chain resistance pattern includes an active layer for receiving an externally applied optical signal, a plurality of conductive layers sequentially stacked on the active layer to form a layer stack, a plurality of contacts, formed between each layer of the layer stack, to electrically connect each pair of adjacently disposed layers of the layer stack, and a pad connected to each layer of the layer stack.

Abstract: A self-aligned bipolar semiconductor device and a fabrication method thereof are provided. After a silicon layer and a collector contact are formed on a buried collector layer, an oxide dummy pattern is formed on the silicon layer to define both an extrinsic base and an intrinsic base. A polycide layer used as the extrinsic base is formed thereon and selectively removed to expose the dummy pattern. After the exposed dummy pattern is removed, an epitaxial layer used as the intrinsic base is grown on both the silicon layer and the polycide layer, and selectively removed from the top of the polycide layer. An oxide layer and a nitride layer are deposited in sequence thereon, and the nitride layer is blanket-etched to form spacers defining an emitter. After a photoresist pattern is formed to mostly cover the oxide layer and partly expose the oxide layer between the spacers over the intrinsic base, the oxide layer is etched by using the photoresist pattern and the spacers as an etch mask.

Abstract: A CMOS image sensor and fabricating method thereof are disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The present invention includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes, an insulating interlayer on a plurality of the inner microlenses, a plurality of metal lines within the insulating interlayer, a device protecting layer on the insulating interlayer, and a plurality of microlenses on the device protecting layer.

Abstract: A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and drain current is increased. The semiconductor device includes an isolation region that, electrically isolates an N-type MOS transistor area from a P-type MOS transistor area, and a nitrade layer formed on an entire upper surface of a substrate, wherein the nitrade layer has silicon ions (Si+) selectively implanted in the P-type MOS transistor area.

Abstract: A lateral double-diffused metal oxide semiconductor transistor (LDMOS) transistor includes a semiconductor substrate of a first conductivity; an extended drain region of the first conductivity formed in a surface region of the semiconductor substrate; and a depletion region, formed in the extended drain region, including first and second impurity regions sequentially embedded below a surface of the extended drain region, the first embedded impurity region being of a second conductivity and the second embedded impurity region being of the first conductivity.

Abstract: A printed circuit board including an opening for receiving a semiconductor package having a plurality of external connections which protrude externally from side surfaces of the semiconductor package. The board also includes a plurality of board connectors electrically interconnected to the plurality of external connections of the package and formed on sidewall of the opening, wiring patterns for electrically interconnect electronic components mounted on the printed circuit board and being electrically interconnected to the plurality of board connectors, a plurality of holes penetrating the printed circuit board, and a fastener inserted into the plurality of holes and for fastening the semiconductor package received in the opening.

Abstract: A CMOS image sensor and fabricating method can reduce leakage current of a photodiode reduced by configuring a triangular shape of a photodiode area to minimize an interface contacting the STI or performing deuterium annealing to remove dangling bonds from an interface contacting with oxide. The CMOS image sensor includes a semiconductor substrate, a device isolation layer on the semiconductor substrate, and a plurality of diodes, each having a shape minimizing an area of a boundary contacting with the device isolation layer.

Abstract: A method of manufacturing a gate in a flash memory device. The method includes forming a stacking structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate on a semiconductor substrate. The further includes removing a remaining portion of the tunnel oxide layer exposed by the control gate by wet etching to a degree that the semiconductor substrate is exposed, and forming an oxide layer covering the exposed portion of the semiconductor substrate and both sidewalls of the floating gate and the control gate.

Abstract: A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. Thus, electric characteristics of the device are enhanced. The semiconductor device includes a substrate having a high-voltage transistor area and a PIP capacitor area, an extended drain region disposed in the high-voltage transistor area and separated from a source region, an impurity region formed in an upper portion of the extended drain region, and a drain region formed on a surface of the substrate and disposed within the impurity region.

Abstract: A method for detecting an abnormal condition of a MOS transistor in a subthreshold region. The method includes measuring a variation in a drain current with respect to a variation of a gate voltage of the MOS transistor to obtain a characteristics curve, and calculating, with reference to the obtained characteristics curve, a variation of transconductance with respect to each of the gate voltages to obtain a transconductance variable curve. The transconductance variable curve is differentiated. A number of inflection points in a curve obtained by the differentiation is determined to indicate the abnormal condition of the MOS transistor.

Abstract: A CMOS image sensor includes a plurality of photodiodes in a semiconductor substrate; an insulating interlayer on the semiconductor substrate including the plurality of photodiodes; a metal line in the insulating interlayer; a passivation layer on the insulating interlayer; an adhesive layer on the passivation layer; and a plurality of micro-lenses on the adhesive layer.

Abstract: A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.

Abstract: A method of pre-treating a wafer surface including loading the wafer into a furnace, purging the furnace to discharge oxygen gas by supplying nitrogen gas, and baking the wafer while hydrogen gas is supplied into the furnace at a defined temperature and for a defined time.

Abstract: A method of manufacturing a semiconductor device includes forming a polysilicon layer on a trench isolation layer and a tunnel oxide layer formed on a semiconductor substrate, and doping the polysilicon layer with germanium or argon. The doped polysilicon layer is patterned to form a floating gate electrode layer pattern. A charge-trapping layer is formed on the floating gate electrode layer pattern, and a control gate electrode layer pattern is formed on the charge-trapping layer.

Abstract: A CMOS image sensor and a method for manufacturing the same improves photosensitivity and prevent loss of light by forming a photo-sensing unit under a color filter. The CMOS image sensor may include a plurality of transistors formed on a semiconductor substrate, a metal line formed over the plurality of transistors for electrically connecting the plurality of transistors, and a plurality of photodiodes electrically connected with the plurality of transistors and formed over the metal line.

Abstract: A semiconductor package device including a lead frame including a die pad to which a semiconductor chip is attached and a plurality of terminals for electrical interconnection of the semiconductor chip to an external device. The device also includes a plurality of bonding wires for electrically interconnecting the terminals to the semiconductor chip, a package body for protecting the semiconductor chip, die pad, terminals, and bonding wires, and a plurality of connections bonded to the terminals for electrically interconnecting the semiconductor chip to the external device. The plurality of connections are made of solder balls or bumps and electrically interconnected to board connectors of an external circuit board.

Abstract: A CMOS ;image sensor and fabricating method thereof can enhance the quality of the image sensor by preventing unnecessary diffused reflection of light by providing an opaque filter layer next to a microlens. The CMOS image sensor includes a photodiode, an insulating interlayer, a metal line, a device protecting layer, a microlens on the device protecting layer and overlapped with the photodiode, and an opaque layer pattern on the device protecting layer next to the microlens.

Abstract: A CMOS image sensor and a method for fabricating the same prevent a lifting effect of microlenses. Also, a diffused reflection of microlenses is prevented. The CMOS image sensor includes photodiodes, an interlayer insulating layer, metal lines formed in the interlayer insulating layer to electrically connect the respective photodiodes with each other, an oxide layer, a passivation layer to protect the CMOS image sensor from external sources, and microlenses formed to pass through the passivation layer at portions corresponding to the photodiodes.