Abstract: A mask ROM, a method for fabricating the same and a method for coding the same are disclosed. The method for forming the mask ROM maximizes packing density and integration of a device. The mask ROM includes a semiconductor substrate having a device isolation region and an active region, BN junction regions formed in predetermined portions of the active region, an insulating film, first electrode layers formed on predetermined portions of the insulating film, spacers formed at sides of the first electrode layers, and second electrode layers between the spacers.

Abstract: A method of forming a gate of a flash memory cell, by which a coupling effect between floating and control gates can be enhanced by forming a polysilicon spacer in forming the floating gate to increase a surface area of the floating gate. The gate is formed by forming a nitride layer pattern on a substrate to define a prescribed space, forming a polysilicon spacer at a sidewall of the nitride layer pattern within the defined space on the first polysilicon, and removing the nitride layer pattern.

Abstract: A wafer transfer apparatus having two independently movable transfer modules. The apparatus that transfers the wafers from one chamber to another includes a first transfer module and a second transfer module. Each module has a robot arm and at least one blade. Each robot arm freely rotates along the chambers, and each blade is rotatably connected to the robot arm. The first and second transfer modules move independently in same or different directions. Each transfer module may have two blades, which are joined respectively to upper and lower parts of the robot arm. Furthermore, the first and second transfer modules can maintain an angle of at least one hundred twenty degrees, whereby preventing the wafers from being overlapped in transit.

Abstract: A variable radix divider uses dividend, divisor and quotient as division operators and includes an adder/subtractor having inputs of the dividend and the divisor. The divider further includes a first and second quotient/radix generator having inputs of the dividend and the divisor, a first multiplexer having input of the output from the first quotient/radix generator, and a second multiplexer having input of the output from the second quotient/radix generator. The first and second generators each includes a prediction adder/subtractor having inputs of bits in prediction range of the dividend and bits in prediction range of the divisor, a radix generator, and a quotient generator. The radix generator and the quotient generator have input of the output of the prediction adder/subtractor. The divider iterates a recursive cycle operation until the division operation through a feedback path to the dividend is completed.

Abstract: A metal-to-metal capacitor including a plurality of first metal blocks formed apart from each other in a vertical direction and arranged in an array format, and a plurality of second metal blocks formed apart from each other in a vertical direction and alternately arranged with the array of the first metal blocks. A first plurality of via contacts interconnect the first metal blocks in a vertical direction and are arranged in parallel, and a second plurality of via contacts interconnect the second metal blocks in a vertical direction and are arranged in parallel.

Abstract: A system and method for simulating a diode device measures electrical characteristics of a plurality of diodes; normalizes the measured electrical characteristics of the diode; extracts a plurality of device parameters of each of the diodes from the normalized characteristics; converts the device parameters of each of the diodes to values per unit area; obtains a linear equation from the converted device parameters; and predicts electrical characteristics of certain diode area from the linear equation and the device parameters. The linear equation is obtained by a least square method of the regression analysis to extract the device parameters of each of the diodes which are converted to value per unit area. The device parameters are obtained by a simultaneous equation which is derived from both a diode having larger area component and a diode having greater length component.

Abstract: A baking apparatus used in a photolithography process of a semiconductor device, and a method for controlling critical dimension of a photoresist pattern using the same. The baking apparatus comprises: a processing chamber; a chuck disposed in the processing chamber on which a semiconductor wafer can be loaded; and a heating means supplying a different temperature of heat by regions of the wafer.

Abstract: A capacitor for a semiconductor device includes a first inter metal dielectric layer is disposed on a substrate. A first electrode is disposed on the first inter metal dielectric layer. A second electrode partially overlaps the first electrode. A first dielectric layer is disposed between the first and second electrodes. A third electrode partially overlaps the second electrode. A second dielectric layer is disposed between the second and third electrodes. An etch stop layer is disposed on the first, second, and third electrodes. A second inter metal dielectric layer is formed on the etch stop layer and includes first, second, and third via holes exposing the first and third electrodes and the etch stop layer. First, second, and third plugs are disposed in the first, second, and third via holes.

Abstract: In order to provide a method for preventing the channel length from being shortened as well as reducing the SAS resistance, the semiconductor device according to the present invention is manufactured by forming continuous linear trench lines on a semiconductor substrate, forming gate oxide lines on the semiconductor substrate between the trench lines, forming gate lines on the trench lines and the gate oxide lines, the gate lines being substantially perpendicular to the trench lines, etching the gate oxide lines and trench lines positioned between the gate lines, to form an etched region forming self aligned sources (SASs) by implanting impurity ions into the etched region, forming spacers on sidewalls of the gate lines, and implanting impurity ions in the SAS region using the spacers as a mask.

Abstract: A CMOS image sensor and fabricating method thereof enable enhanced photo-response characteristics and protect a microlens in packaging by embedding the microlens in a passivation layer pattern. The image sensor may include a semiconductor substrate, a photodiode, a metal line, an insulating layer, a passivation layer pattern, and a microlens formed to be embedded in the passivation layer pattern.

Abstract: A method of manufacturing a semiconductor device including forming a dummy gate electrode which is divided into first and second areas, selectively implanting N-type ions and P-type ions into the first and second areas of the dummy gate electrode respectively and then implanting impurity ions into a boundary region between the first area and second area of the dummy gate electrode.

Abstract: A method for forming shallow trench isolation in a semiconductor device including forming a pad oxide, a pad nitride, and a pore-generating layer on an entire surface of a semiconductor substrate in successive order; etching the pore-generating layer, the pad nitride, the pad oxide and the substrate to form a trench in the substrate; forming a trench oxide over the entire surface of the substrate by a CVD process to fill the trench; and removing the trench oxide in an active device area while retaining the trench oxide in the trench.

Abstract: A system includes a throttle valve moving in response to a pressure present in a vacuum pump line for controlling the pressure of the vacuum pump line based on the movement of the throttle valve; a monometer for detecting the movement of the throttle valve and outputting movement data indicative of the movement of the throttle valve; and a proportional integral derivative controller for generating feedback information based on the movement data output from the monometer.

Abstract: An image sensor includes a color filter layer including a plurality of color filters forming a color filter array of two dimensions; an inner lens layer, disposed below the color filter layer, the inner lens layer including a plurality of inner lenses arranged in a striped pattern in correspondence to a first dimension of the color filter array; and a microlens layer, disposed above the color filter layer, the microlens layer including a plurality of microlenses arranged in a striped pattern in correspondence to a second dimension of the color filter array, each microlens layer having a curved upper surface for focusing light. Thus, the incident light through the condensing lens is induced to photodiodes so as to reduce light loss and improve photosensitivity.

Abstract: A method is provided in which a first oxide layer is deposited on a silicon substrate and etched to form openings. A first silicon epitaxial layer is grown on the substrate in the openings, forming first active regions, a second oxide layer is deposited thereon, and the first and second oxide layers are etched such that the first oxide layer is wholly removed and the second oxide layer remains only on the first silicon epitaxial layer. A third oxide layer is thermally grown on entire resultant surfaces and then blanket-etched to remain only on sidewalls of the first silicon epitaxial layer. A second silicon epitaxial layer is grown on the exposed substrate between the first active regions, thus forming second active regions. The second oxide layer remaining on the first silicon epitaxial layer is removed. The first and second active regions are separated and electrically isolated by the third oxide layer.

Abstract: A lateral double-diffused MOS (LDMOS) transistor is provided with a trench source structure. The LDMOS transistor includes a semiconductor substrate of a first conductivity, the semiconductor substrate having a trench formed in a surface region corresponding to a source of the transistor; a body of a second conductivity, the body disposed in the semiconductor substrate to surround the trench; and a source region of the first conductivity, the source region forming a sidewall of the trench.

Abstract: A method of dual bird's beak LOCOS may reduce a design rule for a more cost-effective logic device formation. The method may also form a LOCOS layer having a smooth bird's beak to fabricate a stable high-voltage device. The method includes steps of defining a low-voltage device area for a logic device and a high-voltage device area for a high-voltage device, forming a first pad layer in the low-voltage device area and a second pad layer in the high-voltage device area, the first pad layer being thinner than the second pad layer, and forming LOCOS type device isolation layers having bird's beaks differing in size in each of the low-voltage device area and the high-voltage device area, by oxidizing a portion of the semiconductor substrate exposed by a hard mask.

Abstract: A method of manufacturing a semiconductor device providing insulation between a plurality of MOS transistors without device isolation regions. The method includes forming a first insulation layer on a substrate, exposing a portion of the substrate by etching the first insulation layer using a resist, growing an epitaxial layer on the exposed portion of the substrate, removing the patterned first insulation layer, and forming transistors on the substrate and epitaxial layer, respectively. The epitaxial layer is grown to a degree that an upper surface of the epitaxial layer is higher than that of the substrate.

Abstract: A manufacturing method of a double LDD MOS transistor includes forming a gate electrode on a semiconductor substrate; forming a first LDD area by implanting and thermally annealing impurity ions using the gate electrode as a mask; forming a first spacer on both lateral walls of the gate electrode; forming a second LDD area by implanting and thermally annealing impurity ions using the gate electrode and the first spacer as a mask; forming a second spacer on both lateral walls of the gate electrode and the first spacer; and forming a source-drain diffusion area by implanting and thermally annealing impurity ions using the gate electrode, the first spacer, and the second spacer as a mask.

Abstract: A method for photomask processing including the formation of a photoresist pattern for a P-Well. The method further includes implanting ions for the P-well using the photoresist pattern as an ion implantation mask, coating another photoresist for the N-well that has a higher etch resistance than that of the photoresist for the P-well, removing the photoresist for the P-well, implanting ions for the N-well, and removing the photoresist. The method reduces the number of photomask processes for ion implantation, so the total processing cost can be reduced.