Abstract: A flash memory device having a reduced source resistance and a fabrication method thereof are disclosed. An example flash memory includes a cell region including a gate, a source line, a drain contact, and a cell trench area for device isolation on a silicon substrate. The example flash memory also includes a peripheral region positioned around the cell region and including a subsidiary circuit and a peripheral trench area for device isolation on the silicon substrate, wherein the cell trench area of the cell region is shallower than the peripheral trench area of the peripheral region.

Abstract: Methods of manufacturing MOS transistors which are capable of suppressing a short channel effect are disclosed. The short channel effect is suppressed by forming source/drain regions of a shallow junction and sufficiently doping a gate. An illustrated method includes: forming a gate insulating layer and a gate on a semiconductor substrate of a first conductivity type; forming lightly doped drain regions of a second conductivity type within the substrate at opposite sides of the gate; forming spacers on side walls of the gate; forming an insulating buffer layer; exposing a top surface of the gate by performing a planarization process on the insulating buffer layer; doping the gate by implanting impurity ions of the second conductivity type into the top surface of the gate; removing the insulating buffer layer; and forming source/drain regions of the second conductivity type within the substrate at opposite sides of the spacers.

Abstract: A method for etching a metal layer on which an oxide-based ARC layer is coated in a semiconductor device comprises the step of performing a dry cleaning process by using a Cl2/CHF3 based gas, after dry cleaning the ARC layer by using the oxide-based gas. As a result, the etching rates of the center area and the edge area are substantially same.

Abstract: The present disclosure is directed to a non-volatile memory device having a SONOS structure and a method of fabricating the same, wherein the non-volatile memory device having the SONOS structure is fabricated using a simple and lower cost method by greatly reducing the number of the photo engraving process.

Abstract: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride layer are deposited on the surface of the substrate including the trench. A spacer is formed on the lateral walls of the trench by etching the second nitride layer. A buried oxide is grown in the substrate underneath the trench by performing thermal oxidation on the substrate. The trench is then filled by depositing an insulating layer after removing the spacer and performing a planarization process. The STI fabricating method can reduce substantially a total parasitic capacitance. Therefore, gate RC delay is reduced and the operating speed of a transistor increases.

Abstract: An STI structure and fabricating method thereof are disclosed. The STI fabricating method comprises forming a pad oxide layer and a first nitride layer on a substrate. A trench is formed by etching the first nitride layer, the pad oxide layer and the substrate. An oxide and a second nitride layer are deposited on the surface of the substrate including the trench. A spacer is formed on the lateral walls of the trench by etching the second nitride layer. A buried oxide is grown in the substrate underneath the trench by performing thermal oxidation on the substrate. The trench is then filled by depositing an insulating layer after removing the spacer and performing a planarization process. The STI fabricating method can reduce substantially a total parasitic capacitance. Therefore, gate RC delay is reduced and the operating speed of a transistor increases.

Abstract: A device isolation structure of a semiconductor device may be a silicon wafer, a trench formed in the silicon wafer to have a predetermined depth, a first thermal oxide layer formed to an inner surface of the trench, a pad oxide layer formed on the silicon wafer, a second thermal oxide layer formed on the pad oxide layer and having a round side adjacent to an opening of the trench, and a field oxide layer filled in the trench having the first thermal oxide layer.

Abstract: The present invention relates to a semiconductor device and a method for fabricating a contact of the semiconductor device, and in particular, to the method for fabricating a semiconductor contact of the device for electrically coupling upper and lower metal wires or coupling an electrode and a metal wire and a method for fabricating the contact. The method includes forming an interlayer insulating layer on a semiconductor substrate; forming a contact hole by selectively removing the interlayer insulating layer; forming a barrier metal layer on a surface of the interlayer insulating layer, increasing roughness of a surface of the barrier layer at an area around an inlet of the contact hole; and forming a contact by filling the contact hole with a conductive material. According to this method, the conductive layer is slowly deposited around the inlet of the contact hole relative to the other areas of the contact bole, such that it is possible to form a void free contact with a high aspect ratio.

Abstract: A method of forming a bonding pad of a semiconductor device is disclosed. An example method forms a first insulating layer over a semiconductor substrate, forms a trench by removing some part of the first insulating layer, forms a top metal interconnect in the trench, forms a second insulating layer over the substrate including the top metal interconnect, and forms a contact hole by removing some part of the second insulating layer, the contact hole exposing a portion of the top metal interconnect. In addition, the example method forms a metal layer on the surface of the second insulating layer and the sidewalls and bottom of the contact hole, forms a metal pad by removing some parts of the metal layer, forms a third insulating layer over the second insulating layer and the metal pad, and exposes the metal pad on the second insulating layer by removing some part of the third insulating layer.

Abstract: A semiconductor device which effectively reduces copper oxide layers on copper conductive lines is disclosed. The method includes forming a first insulating layer on a semiconductor substrate; forming a first conductive line by depositing a conductive material on the first insulating layer and selectively patterning the conductive material. A second insulating layer is deposited on top of the substrate including on the first conductive line. A via hole is formed by selectively patterning the second insulating layer to expose a certain portion of the first conductive line. A natural oxide layer is removed by plasma-processing the natural oxide layer using H2+CO gas.

Abstract: A method for manufacturing a semiconductor device includes forming a barrier layer on an individual device formed on a semiconductor substrate and including a MOS transistor. An ozone process is performed on the barrier layer. A pre-metal dielectric (I?MD) layer is then formed on the barrier layer.

Abstract: A MOS transistor and a method for fabricating the MOS transistor. The present invention enables implementation of a stable semiconductor device that is capable of protecting against leakage current generation by improving the “LDD effect” and securing a large process margin by adjusting an “off” current. The method for fabricating a MOS transistor includes placing or arranging an epitaxial layer between a silicon wafer and a gate electrode, and forming three impurity regions, including a very low concentration impurity region, and a low concentration impurity region and a high concentration impurity region (source and drain region).

Abstract: The present invention can protect from degradation of product reliability of a semiconductor caused during formation of a salicide suppression layer. In order to achieve this, unlike the conventional method in which the sidewall spacer of the gate electrode and the salicide suppression layer in the non-salicide region are formed through two etching processes, the salicide suppression layer and the sidewall spacer are formed at the same time with one etching process after the salicide suppression substance and the sidewall spacer substance are sequentially formed in the present invention, such that it is possible to efficiently prevent an undercut effect from occurring at the spacer side during the etching process for forming the salicide suppression layer, and to effectively prevent the surface of the semiconductor substrate from being damaged.

Abstract: A method of fabricating a metal interconnection of semiconductor device is disclosed. A metal interconnection fabricating method according to the present invention comprises the steps of depositing a metal layer on a substrate having a predetermined structure; patterning a bottom metal layer through etching the metal layer; forming a pad electrically connecting the bottom metal layer to a scribe area; forming an insulating layer on the substrate including the bottom metal layer; forming a via hole and a trench, in which an upper metal layer is formed, on the insulating layer, the via hole connecting the bottom metal layer with the upper metal layer; forming a plating layer by means of electroplating; and performing a planarization process for the plating layer. Accordingly, the present invention needs not a separate seed layer because the bottom metal layer is used as a seed layer.

Abstract: The present invention is directed to a method of forming a gate electrode in a semiconductor device, which is capable of reducing a line width of the gate electrode by performing a photolithography process after defining a wide region on which a gate electrode is located on a photoresist twice such that the line width of the gate electrode is not subject to a wavelength of a light source used when the photolithography process is performed.

Abstract: Method for forming intermetal dielectric layer is disclosed including steps of: preparing a substrate with wiring on a lower insulating layer, the wiring having a plurality of separating portions; forming first and second water marks on the lower insulating layer located in the separating portions and on upper surfaces of the wiring; transforming the first and second water marks into first and second air bubbles, respectively; depositing a first insulating layer of lower dielectric constant on the whole surface of the substrate, and at the same time, forming first and second air gaps by growing said first and second air bubbles on and between the wirings, respectively; removing the upper portion of the first insulating layer to make open the second air gap; and depositing a second insulating layer of lower dielectric constant on the first insulating layer to fill the opened second air gap.

Abstract: Methods for manufacturing semiconductor devices are disclosed. In a disclosed method, a first nitride layer and a device isolation oxide layer are etched to thereby expose a portion of a silicon substrate where an active region is to be formed. An epitaxial growth is performed on the active region and a first oxide layer is deposited thereon. Portions of the first oxide layer where a source and a drain are to be formed are etched. The first oxide layer deposited on the portions where the source and the drain are to be formed is then etched. An epitaxial growth is performed on the portions where the source and the drain are to be formed to thereby form the source and the drain. A second nitride layer is deposited thereon. A portion of the first oxide layer located where a gate is to be formed is etched using a gate mask. A third nitride layer is deposited on the source, the drain, and the exposed active region and then etched back to thereby form a nitride layer to control a length of the gate.

Abstract: The present invention relates to a CMP (chemical mechanical polishing) slurry composition and a method for planarizing a semiconductor device. The CMP composition comprises fumed silica, tetramethyl ammonium hydroxide, phosphates, fluorine compounds and deionized water. The method of planarizing comprises the steps of etching, subsequently laminating and polishing a semiconductor device by said CMP slurry composition.

Abstract: Semiconductor devices and methods to form a trench in a semiconductor device are disclosed. A disclosed process comprises: forming a hollow by etching a portion of a semiconductor substrate; forming a side wall layer in an inner side wall of the hollow; forming a trench by further etching the semiconductor substrate exposed through the bottom of the hollow; and filling the trench by forming an insulation film on the side wall layer and the trench.

Abstract: A method for forming dual gate electrodes using a damascene gate process is disclosed.