Abstract: A system for real-time simulation of a battery comprising simulating a cell array by an overall computer model is disclosed. The model includes a plurality of single cells. A computer is connected via a cell voltage emulator to a control unit calculating terminal voltages of single cells by using the overall model and supplying the calculated terminal cell voltages to the control unit by the cell voltage emulator. The overall model comprises a first model which models a first single reference cell having cell parameters typical of the cell array and sending the total input current of the cell array to the first model as an input variable. The terminal voltage of the reference cell is calculated by the first model. The overall model further comprises a second model which calculates a deviation in the terminal voltage of an additional single cell from the terminal voltage of the reference cell.

Abstract: A configuration tool includes a tangible, non-transitory computer-readable medium having computer-executable instructions for configuring a model of a technical system and displaying the model on a display connected to a computer. The model includes at least two model components. Each model component has at least one port. Each model component is displayable in an expanded component representation on the display. The at least one port of each model component is connectable to at least one port of another model component by port association lines. Each model component is displayable in an expanded line representation on the display along with the at least one port and the port association lines of each model component. At least for one selected model component the port association lines connected to ports of the selected model component can be selected to be displayed in a reduced line representation.

Abstract: An apparatus for measuring electrical variables includes an external measuring connection, and a converter that converts a plurality of measurement variables into respective electrical measurement variables of a single predefined type. A control device for controlling the converter is provided and at least one type of variable to be measured with the converter can be selected via the control device, and a converter for at least two types of variables to be measured respectively has at least one independent input stage that can be used to detect the measurement variable of the type to be measured and to convert it into a predefined or predefinable type of variable. An electrical signal provided at the measuring connection is analysed in a parallel manner with respect to at least two different criteria via at least two input stages for different types of variables to be measured.

Abstract: A configuration device for the graphical creation of at least one test sequence for controlling a test device having at least one electronic computer. The test device is controllable according to the created test sequence. The configuration device has at least one display device, graphical library functional elements being displayed with the display device in a library field. The test sequence can be created by placing at least one instance of a library functional element in a configuration field. The instance of a library functional element is placed in the configuration field. The graphical library functional element can be provided with a function placeholder, whereby the function placeholder in the instance of the library functional element can be provided with an instance functionality, whereby the reference of the instance of the library functional element to the library functional element is retained.

Abstract: A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.

Abstract: A test device for testing at least a portion of a virtual electronic control unit with a simulation environment in a simulator, having the virtual electronic control unit and the simulation environment. The virtual electronic control unit has a software component with an external data interface. The simulation environment has a data interface for direct data exchange with the virtual electronic control unit. A test device with reduced adaptation effort is implemented via a virtual electronic control unit pin module that has at least one virtual electronic control unit interface and is connected via the virtual electronic control unit interface to the external data interface of the software component of the virtual electronic control unit.

Abstract: A test device for testing at least a portion of a virtual control unit with a simulation environment in a simulator, having the virtual control unit and the simulation environment. The virtual control unit has at least one software component with an external data interface. The simulation environment has a data interface for indirect data exchange with the virtual electronic control unit. A reduced dependency between the virtual control unit and the simulation environment with the result that electrical fault simulation with virtual electronic control units is possible in a simpler way, is achieved in that a virtual control unit pin module and a virtual manipulation unit are additionally provided between the virtual control unit and the simulation environment, the two units transmit a virtual physical control unit signal through a virtual control unit pin of the virtual electronic control unit pin module. The virtual manipulation unit outputs a manipulated virtual physical control unit signal.

Abstract: A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.

Abstract: A method for estimating a resource consumption of storage space and/or of required runtime of a control device program code to be generated for a control program, whereby the functionality of the control program is given in an executable model. The model has a function with first functional magnitudes and first information associated with the first functional magnitudes and optimization parameters for optimizing a code generator. A program code representation is generated for part of the model comprising the function by the code generator taking into account first values of the optimization parameters. An estimation unit comprises a resource model with hardware parameters. An estimated value for the storage space requirement is determined for the control device program code and/or a runtime estimated value is determined for the control device program code by the estimation unit taking into account the hardware parameters and based on the program code representation.

Abstract: A method for performing configuration of a control unit test system with hardware components connected thereto, wherein control units can be tested with the test system in an environment simulated by the test system by means of a model, and wherein the test system comprises at least one computer, in particular a computer executing the model, as well as hardware components, connected to one another by means of at least one network, in which at least a portion of the hardware components comprises a dedicated server (MIS) that, by means of communication, provides access to the configuration data associated with the hardware component, in particular stored in the hardware component, and the model and/or the hardware component is adapted, in particular configured, as a function of the configuration data that are made accessible.

Abstract: A method is provided for processing data in an influencing device, whereby the influencing device is connected to a vehicle control unit and to a data processing unit. The vehicle control unit and the influencing device are disposed in a motor vehicle or, for example, on a test bench in a laboratory. A first program runs in the vehicle control unit. Data are exchanged according to an XCP protocol and/or a CCP protocol between the data processing unit and the influencing device. The influencing device has a second execution unit, which executes predetermined data processing steps more rapidly than the first execution unit. The data exchanged by the XCP protocol or the CCP protocol are checked for a predetermined criterion and, based on the result of the check, the data are processed either in the first execution unit or in the second execution unit.

Abstract: A method for performing an inventory of the hardware components connected to a control unit test system, wherein control units can be tested with the test system in an environment simulated by the test system by means of a model, and wherein the test system comprises at least one computer) and hardware components that are connected to one another by means of at least one network. For at least a portion of the hardware components, in particular of all simulation-specific hardware components, at least one item of component information that uniquely and digitally identifies the hardware component is read therefrom, and all identifying component information that has been read out is stored.

Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.

Abstract: A method for manipulating a memory operation of a control unit program on a memory of a virtual or real electronic control unit (ECU), such as is used in vehicles, for example. The manipulation of the memory operation is accomplished by a memory manipulation program component, via which a set of manipulation functions is provided, from which at least one manipulation function is selected, so that this function, by activating the memory manipulation program component, changes a memory access initiated by the control unit program in accordance with the selected manipulation function during execution of the control unit program.

Abstract: A computer-implemented method for data management of product variants in control unit development is provided. Consistent data management is ensured by initially specification of product features in a variant model, specification of components in at least one domain, and definition of feature/component dependencies by associating components with at least one product feature, and subsequently specification of at least one product variant of interest by selecting product features, specification of at least one domain of interest, automated identification of the components pertaining to the product variant of interest through automated evaluation of the feature/component dependencies, and automated output of the identified components.

Abstract: A circuit arrangement for connecting a bus participant to at least one bus, having an interface for connecting the bus participant to the circuit arrangement, a first bus input, and a first bus output between which the bus participant is switchable via the interface. The circuit arrangement includes a second bus input and output for connecting the bus to the circuit arrangement in a ring topology in such a way that the first bus output is connected at least indirectly to the second bus input and the second bus output is connected at least indirectly to the first bus input via the bus. The bus in the circuit arrangement can be separated to obtain a line topology and can be configured as bus-terminating at one of the bus inputs or bus outputs. A system for the functional testing of bus participants on a bus in a simulation environment is provided.

Abstract: The invention relates to a method for testing the compatibility between two software components of a control device network, a technical interface description being assigned to each software component, this interface description having a specified description standard, and each description standard having a hierarchical position in an hereditary hierarchy of all possible description standards. The common description standard, which is nearest in the hereditary hierarchy, of the software components to be compared is determined based on the hereditary hierarchy, and the common portion of the respective interface descriptions is determined based on the common description standard of the common portion of the respective interface descriptions and compared with one another.

Abstract: A procedure for generating an executable overall control program such as a measurement, control, regulation and/or calibration is illustrated and described for controlling a control system having at least one electronic processor unit, whereby multiple functional model components of one of the functional models describing the functionality of the overall control program are compiled in data code, the data elements used in the functional model components are listed at least partially in one of the various data element sets of the functional model. References between data elements in the data element set and those functional model components of the functional model in which the data elements are used are registered, and these references are saved as additional reference information.

Abstract: A method for editing a computer-aided design model for developing electronic control units in a design environment, whereby the design model comprises at least one model object with first data. The method begins with the reading of all model objects of the design model and the reading of an allocation list, which assigns a particular globally unique key to each model object. If the first data are available, the reading of the first data from a first memory location follows. Then, assignment of the first data to the model object based on the globally unique key occurs, so that the first data are available during editing of the design model. If the first data are not available, assignment of the globally unique key to the model object occurs, so that the globally unique key is available during tediting of the design model.

Abstract: A method for the computer-aided generation of at least one part of an executable control program, particularly a measuring, control, regulating, and/or calibration program, for controlling a control system having at least one electronic processor unit is provided. The functionality of the control program is described at least partially in at least one graphical model and the graphical model is divided in hierarchical levels into submodels. A submodel can be divided nested into submodels of a lower hierarchical level, whereby values for options for the compiling of the graphical model to program code are preset and program code is generated from the model co-compiled to the executable control program. Values for options for the compiling of the graphical model to program code and to the executable control program can be preset thereby granularly with the automatic avoidance of conflicting presettings of values for these options.