Abstract: A method for changing software in a memory of an electronic control unit, wherein each memory address from the overlay memory can be assigned to a memory address in the read-only memory by an assignment information item. During a run time of the control unit, at least a functional part of a bypass routine that is to at least partially replace an original program routine is stored in an address range in the overlay memory, or a jump instruction is stored in the overlay memory as the first part of a bypass routine that refers to a second part of the bypass routine that is stored in an address range accessible to the processor. To activate an overlay functionality the address and/or the address range of the overlay memory are assigned to an address or address range of the program routine to be replaced.

Abstract: A simulation apparatus for simulating a peripheral circuit arrangement connected to a regulating device and has a first current controller for influencing a first load current and a second current controller for influencing a first source current. The first current controller is controlled by a model code and used to set the first load current, and the first load current is routed to a first load connection of the regulating device. The second current controller is controlled by the model code and used to set the first source current, which is routed to a first supply connection of the regulating device. The model code influences the model code on the first current controller and the second current controller allows the first load current to be recovered at least proportionally from the first source current and/or the first source current to be recovered at least proportionally from the first load current.

Abstract: A method in which the propagation times of a target network are simulated in an actual network, wherein the topology of the target network includes a number of senders and a number of receivers, and wherein the topology of the actual network includes one or more of the senders and receivers. A path between a first sender and a first receiver in the topology of the actual network differs from the path between the first sender and the first receiver in the topology of the target network, wherein in the actual network at least one first message of the first sender is received through a first network interface by a gateway having at least two network interfaces, is delayed by a delay, and is sent through a second network interface on a path to the first receiver.

Abstract: A method for accessing signals of a programmable logic device having a functional level and a configuration level at run time when the programmable logic device is executing a predefined configuration. An access to at least one signal value that has a number of bits is requested. The individual bits in the configuration are each located in an address unit with one address offset apiece such that one or more bits of a signal value are located in one address unit. A bitwise access to the requested signal values takes place, wherein the accesses to the individual bits are sorted as a function of the address unit containing the applicable bit in such a manner that the accesses to all bits located in an address unit take place in sequence as a function of the address offset, independently of the signal containing the applicable bit.

Abstract: A method for determining the power consumption of a programmable logic device, in which at least one configuration parameter is determined in accordance with a predefined configuration and at least one device parameter is determined in accordance with the programmable logic device. The predefined configuration is designed such that the programmable logic device exchanges data with a computing unit through at least one interface pin and receives data from at least one signal source and/or sends it to at least one signal receiver through at least one interface pin. At least one data characteristic of the data exchanged between the computing unit and the programmable logic device as well as at least one signal characteristic of the data received from the at least one signal source and/or sent to the at least one signal receiver are determined.

Abstract: A method for performing an inventory of the hardware components connected to a control unit test system, wherein control units can be tested with the test system in an environment simulated by the test system by means of a model, and wherein the test system comprises at least one computer) and hardware components that are connected to one another by means of at least one network. For at least a portion of the hardware components, in particular of all simulation-specific hardware components, at least one item of component information that uniquely and digitally identifies the hardware component is read therefrom, and all identifying component information that has been read out is stored.

Abstract: A method for accessing signals of a programmable logic device having a functional level and a configuration level at run time when the programmable logic device is executing a predefined configuration. An access to at least one signal value that has a number of bits is requested. The individual bits in the configuration are each located in an address unit with one address offset apiece such that one or more bits of a signal value are located in one address unit. A bitwise access to the requested signal values takes place, wherein the accesses to the individual bits are sorted as a function of the address unit containing the applicable bit in such a manner that the accesses to all bits located in an address unit take place in sequence as a function of the address offset, independently of the signal containing the applicable bit.

Abstract: An arrangement for testing a control unit via a test environment, having a computer-based test management tool, wherein the test management tool is configured for model-based development and/or management of at least one test plan implemented as a data structure in order to test the control unit, and the test plan has at least one test and a start condition for initiating execution of the test plan; a computer-based test execution control tool, wherein the test execution control tool is configured to initiate execution of the test plan on the test environment when the start condition is met; and a computer-based database, wherein the database is configured to store the test plan implemented as a data structure and is also configured for shared, common access to the test plan by the test management tool and the test execution control tool.

Abstract: A method for real-time testing of a control unit for an internal combustion engine using a simulator is provided. The control unit and the simulator are connected to one another by a first data channel. The control unit transmits engine control data to the simulator through the first data channel and the simulator calculates engine state variables in real time on its first simulator processor with a first sampling step size and transmits at least some of the engine state variables to the control unit. Thus, selected engine state variables can be made available at a different frequency, and in particular at a higher frequency, than is possible by the first sampling step size of the first simulator processor, in that the simulator calculates at least one specific engine state variable using a partial engine model and with a second sampling step size different from the first sampling step size.

Abstract: A method for editing a computer-aided design model for developing electronic control units in a design environment, whereby the design model comprises at least one model object with first data. The method begins with the reading of all model objects of the design model and the reading of an allocation list, which assigns a particular globally unique key to each model object. If the first data are available, the reading of the first data from a first memory location follows. Then, assignment of the first data to the model object based on the globally unique key occurs, so that the first data are available during editing of the design model. If the first data are not available, assignment of the globally unique key to the model object occurs, so that the globally unique key is available during tediting of the design model.

Abstract: A method for providing a timestamp in a real-time system, whereby the real-time system has an FPGA and a CPU, which cooperate with one another, and at least one register, which contains a system time, is implemented in the FPGA. The method includes the steps of providing a CPU counter for the system time, which is driven by a clock signal of the CPU, providing a synchronization counter in the CPU, whereby the synchronization counter is driven by a clock signal of the CPU, reading of the counter for providing the system time by a real-time application, querying the synchronization counter in the real-time application, and synchronizing the counter with the system time in the real-time application, when the synchronization counter outputs a value that corresponds to more than a predefined time period since the last synchronization of the CPU counter with the system time.

Abstract: A computer-implemented method for generating control unit program code. The control unit program code or an intermediate representation in the generation of the control unit program code is generated from at least one first data object with at least one first software tool. The first software tool outputs at least one message about the generation process during the generation of the control unit program code or the intermediate representation, and a computer-implemented message management environment acquires the message output by the software tool. The evaluation of the messages output by the software tools during the generation process is achieved in a more effective manner in that a qualification for the acquired message at least as open or approved is acquired by the message management environment and in that a qualification precondition for a message qualified as approved is also acquired by the message management environment.

Abstract: A method for automatic connection of model components of a model of a technical system on a computer with a display, wherein the model has a first model component and a second model component. The first model component and the second model component each have at least one hierarchy element, wherein a hierarchy element contains no hierarchy element, or one hierarchy element, or multiple hierarchy elements. A hierarchy element has no port, or one port, or multiple ports, wherein a hierarchy element and a port have an identifier. A connection between two ports represents an assignment in the technical system. A first set of hierarchy elements and/or ports and a second set of hierarchy elements and/or ports is selected through a graphical user action, wherein a possible assignment is tested for a first port of the first set and a second port of the second set.

Abstract: A method for connecting models of technical systems in a testing device equipped for control unit development having a connection of a first model of a first technical system to a second model of a second technical system. The first model and the second model include a model of a control unit, a model of a technical system to be controlled, or a model of an environment interacting with the control unit or with the technical system to be controlled. The first model has a first data interface and the second model has a second data interface. The method has the provision of a first model hierarchy structure and the provision of a second model hierarchy structure. The method has an automatic configuration of compatible connections so that the first model present in the testing device exchanges data with the second model present in the testing device through compatible connections.

Abstract: A method for emulating a three-phase, brushless DC motor using a load emulator that is connected in a three-phase manner via load terminals to supply terminals of a motor control unit. The load emulator has emulator power electronics and an emulator control unit for controlling the emulator power electronics. The emulator control unit determines the supply terminals that are actuated by the motor control unit and the supply terminals that are not actuated, and the emulator power electronics are actuated by the emulator control unit in such a way that phase currents calculated by the emulator control unit on the basis of a motor model flow in the supply terminals that are actuated by the motor control unit and a phase voltage calculated by the emulator control unit on the basis of a motor model is applied to the supply terminal that is not actuated by the motor control unit.

Abstract: A method is provided for connecting an input/output interface of a tester equipped for control unit development to a model of a technical system present in the tester using an already-existing basic test model of a control unit. The input/output interface is designed for connecting a hardware implementation of the control unit or for connecting a technical system to be controlled, and the model to be connected to the input/output interface is a test model of the technical system to be controlled or a test model of the control unit. The already-existing basic test model of the control unit is accessed, and at least one communication requirement is extracted from the basic test model of the control unit.

Abstract: A method for calculating a desired trajectory for a vehicle is provided. The vehicle is located at a position on a road bounded by two road edges, wherein the road edges are known at least in a region around the position of the vehicle. A spring-mass model is introduced, wherein the spring-mass model is used for calculating the desired trajectory, wherein the positions of the point masses are calculated for a rest state of the spring-mass model, and the calculated positions of the point masses are used as data points for the calculation of a curve connecting the point masses, whereby the curve represents the desired trajectory.

Abstract: A computer-implemented method for editing data object variants of at least one software tool is described and presented, whereby the data object variants have at least one common software/hardware attribute and in each case a configuration of the attribute. It is possible to react to changing configurations of hardware attributes of different data object variants and thereby to changing matching groups during the editing of a data object variant in that for at least one attribute matching configurations of the attribute in different data object variants are captured and that for the attribute information on matching groups of data object variants is stored with the matching configurations of the attribute.

Abstract: A computer-implemented method for implementing a V2X application on target hardware having a radio adapter, wherein the V2X application is modeled in the form of a block diagram by means of a graphical modeling environment and the block diagram is compiled into a V2X program that can be executed on the target hardware and the V2X program is transferred to the target hardware and executed there. The method for implementing a V2X application is realized in an especially simple and advantageous manner in that a V2X communication block that has at least one radio adapter interface, by means of which data are exchanged between the radio adapter and the V2X communication block, is used to create the block diagram.

Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.