Patents Assigned to dSpace GmbH
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Patent number: 12229987Abstract: A method for determining an ego pose of a mobile system and creating a surfel map of a surrounding area of the mobile system via an optimization problem represented by a factor graph includes the steps of: receiving environment sensor data generated by an environment sensor attached to the mobile system, wherein the environment sensor surveys the surrounding area of mobile system, and wherein the environment sensor data represent the surrounding area of the mobile system as a point cloud; generating surfels by converting the point cloud of the received environment sensor data into surfel data; identifying new surfels and known surfels in the generated surfels by comparing the surfel data with the surfel map; and adding a surfel factor for the known surfels to the factor graph and/or adding a surfel node and a surfel factor for the new surfels to the factor graph.Type: GrantFiled: March 5, 2024Date of Patent: February 18, 2025Assignee: DSPACE GMBHInventors: Tobias Biester, Boris Neubert, Veith Roethlingshoefer
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Patent number: 12229530Abstract: A computer-implemented method generates program code of an executable control program for controlling a control system. Functionality of the control program is described at least in part in a graphical model. The graphical model is translated into program code in a text-based programming language. The method includes: generating a first placeholder representing a variable, the first placeholder being used in a predetermined segment of the program code; generating a second placeholder, which is placed before a beginning of the predetermined segment of the program code that uses the first placeholder; and generating a third placeholder, which is placed after an end of the predetermined segment of the program code that uses the first placeholder.Type: GrantFiled: October 21, 2022Date of Patent: February 18, 2025Assignee: DSPACE GMBHInventors: Michael Mair, Lars Wallbaum
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Publication number: 20250055921Abstract: A computer-implemented method for data transfer in a network system comprising an external network and an internal network. The external network including at least one first network element and an external network communication element. The internal network including at least one second network element and an internal network communication element. The second network element being designed to communicate solely within the internal network. The data to be sent is encoded and transferred to the external network communication element. The data is transferred to the internal network communication element via the IP communication channel and decoded. The data is re-encoded into an application layer by the internal network communication element and transferred to the second network element.Type: ApplicationFiled: June 14, 2024Publication date: February 13, 2025Applicant: dSPACE GmbHInventors: Stephan SCHEDLER, Hendrik KASSNER
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Patent number: 12223301Abstract: A method for generating source code includes: transforming a block diagram into an intermediate representation, wherein transforming the block diagram into the intermediate representation comprises transforming at least two blocks, wherein at least one loop results from transforming an operation block; identifying at least one candidate loop in the intermediate representation, wherein a loop body of a candidate loop comprises at least one instruction that accesses the array variable; identifying at least one parallelizable loop from the at least one candidate loop; determining build options for the at least one parallelizable loop and the array variable; inserting build pragmas based on the determined build options in the intermediate representation; and translating the intermediate representation into the source code.Type: GrantFiled: March 17, 2023Date of Patent: February 11, 2025Assignee: DSPACE GMBHInventors: Joerg Niere, Kingshuk Karuri, Pubali Mazumder
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Patent number: 12216967Abstract: A computer-implemented method for real-time simulation of the operation of a specific electric motor by a simulator arithmetic unit comprising a programmable logic device on which a generic motor model is implemented. The method includes: providing a generic system of equations corresponding to the generic motor model; receiving specific information corresponding to the specific motor to be simulated for the generic system of equations and inputting this information into the generic system of equations; generating a specific library containing at least some of the arithmetic operations required for the matrix operations for calculating the operation of the specific motor; implementing references in the generic motor model to the arithmetic operations of the specific library required for real-time simulation of the operation of the specific electric motor; and simulating the operation of the specific electric motor by running the generic motor model on the simulator arithmetic unit.Type: GrantFiled: April 23, 2021Date of Patent: February 4, 2025Assignee: dSPACE GMBHInventor: Bjoern Bobe
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Publication number: 20250021462Abstract: A computer system for error-free execution of multiple computer-controlled build and/or initialization steps for an FPGA-based application. The computer system being set up to generate an FPGA program code as part of build steps, to transfer it to a controlled FPGA and to prepare it for execution within the framework of initialization steps. The computer system is also set up to store and/or to check results of the build and/or initialization steps centrally in a writable memory and to check whether at least one previous build and/or initialization step has been completed without errors by reading out the writable memory before a build and/or initialization step and/or before the execution of the initialization program code. This provides a computer system that avoids the disadvantages of the conventional art.Type: ApplicationFiled: July 12, 2024Publication date: January 16, 2025Applicant: dSPACE GmbHInventors: Heiko KALTE, Dominik LUBELEY
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Patent number: 12197336Abstract: In an FPGA, a memory of the FPGA is to be effectively increased. This is achieved by a computer-implemented method for implementing a model-adaptive cache memory having a model state-dependent memory look-ahead on the FPGA.Type: GrantFiled: June 22, 2023Date of Patent: January 14, 2025Assignee: dSPACE GMBHInventors: Heiko Kalte, Dominik Lubeley
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Publication number: 20250005230Abstract: A computer-implemented method for testing an ECU with a simulator is described and presented. The simulator numerically computes a mathematical environment model on a computational unit. The environment model simulates the environment of the ECU at least in part. The ECU and the simulator are coupled with each other via appropriate I/O interfaces and interact with each other. A matrix-vector multiplication is performed when the environment model is numerically computed on the simulator, in which a matrix is multiplied by a vector to form a result vector. The matrix-vector multiplication is broken down into a sequence of summations by two summands, wherein each summand is a product of two factors, one factor being an element of the matrix and the other factor being an element of the vector.Type: ApplicationFiled: July 1, 2024Publication date: January 2, 2025Applicant: dSPACE GmbHInventors: Axel KIFFE, Thorben HOFFSTADT
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Patent number: 12181505Abstract: A system for measuring the transfer function on a path from a feed antenna via a reflector to a radar sensor testing zone includes: an anechoic chamber; the feed antenna, wherein the feed antenna is configured to transmit and receive a radar signal, and wherein the feed antenna is disposed, together with the reflector, within the anechoic chamber; the radar sensor testing zone, wherein the radar sensor testing zone is a predetermined area within the anechoic chamber; and a retroreflector disposed in the radar sensor testing zone, wherein the retroreflector is configured to cause at least a portion of a measurement signal in the radar frequency range to be reflected back to the feed antenna via the reflector, wherein the measurement signal is received from the feed antenna via the reflector.Type: GrantFiled: April 4, 2023Date of Patent: December 31, 2024Assignee: DSPACE GMBHInventors: Fabian Happ, Andreas Himmler, Jeffrey Paul
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Publication number: 20240427021Abstract: A real-time simulation of a laser beam scanning of a complex of small objects. The device includes a virtual environment with a monolithic 3D model of the complex of small objects, and a sensor simulation for simulating a sensor for measuring distance with the aid of a laser beam. A ray casting routine simulates a laser beam. A distortion routine ascertains an angle of incidence of the laser beam on a surface of the 3D model and selects an intensity distribution assigned to the ascertained angle of incidence from a database. An intensity portion of a reflection of the laser beam is read out as a function of a penetration depth of the laser beam into the complex of small objects. The distortion routine calculates a distorted distance measurement to simulate a plurality of reflections of the laser beam on a plurality of small objects.Type: ApplicationFiled: June 26, 2024Publication date: December 26, 2024Applicant: dSPACE GmbHInventors: Christoph BRODEHL, Christian ESCH, Erik KUEHN
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Publication number: 20240412625Abstract: A computer-implemented method and system for classifying a predefined traffic situation comprised by a data record of environment data of a motor vehicle, with an application of a directed graph to the first data record. Nodes of the directed graph segment the first data record in each case into at least one segment of a movement behavior of the ego vehicle and/or the fellow vehicle relative to a vehicle environment according to a first condition satisfied in a time interval comprising edges of the directed graph symbolizing links between the respective nodes. The predefined traffic situation is classified if all of the specified segments meet a second condition of the predefined traffic situation. A class is outputted representing the predefined traffic situation and/or a respective start and end time of the second data record comprising a segment representing the predefined traffic situation.Type: ApplicationFiled: June 7, 2024Publication date: December 12, 2024Applicant: dSPACE GmbHInventors: André ROSSI, Luka KARAMAN, Philipp ATORF, Jakov TOPIC, Cathrina SOWA
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Patent number: 12158849Abstract: A method is provided for data communication between at least one subregion of an FPGA and another region, in which the data communication is resource efficient. This is achieved by the fact that the data communication, i.e., the reading and writing of a Block RAM from a location to any Block RAM or from any Block RAM to any Block RAM of the FPGA takes place via command sequences of an internal configuration interface of the FPGA.Type: GrantFiled: December 15, 2022Date of Patent: December 3, 2024Assignee: dSPACE GMBHInventors: Heiko Kalte, Dominik Lubeley
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Publication number: 20240385953Abstract: A test system for applying a method for resource-optimized parameter variation of scenarios for testing at least one real and/or virtual system under test and/or for displaying test results. At least one scenario is provided, wherein the scenario is defined by at least one parameter and wherein the parameter is configured by at least one numeric value and/or text value, wherein the numeric value and/or the text value is configurable by additional numeric and/or text values. At least one scenario-based test is performed, wherein the scenario is defined by and is varied over configured parameters. The test results is outputted.Type: ApplicationFiled: May 17, 2024Publication date: November 21, 2024Applicant: dSPACE GmbHInventors: Thomas MISCH, Simon GORDON
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Publication number: 20240385290Abstract: A test arrangement for testing a surroundings sensor. The test arrangement includes a receptacle for the surroundings sensor, which is configured to emit a surroundings signal. A first object simulator is configured to receive the surroundings signal as a first receive signal. A second object simulator is configured to receive the surroundings signal as a second receive signal. A processor is configured to ascertain a signal difference, in particular, a phase difference and/or a frequency difference, from the first and second receive signals, and to ascertain, as a function of the signal difference, a spatial relationship between the surroundings sensor, the first object simulator, and/or the second object simulator.Type: ApplicationFiled: May 15, 2024Publication date: November 21, 2024Applicant: dSPACE GmbHInventors: Juergen SCHMIDT, Tim FISCH, Bernd STELLING
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Patent number: 12124290Abstract: A method for inputting and/or outputting signals having a selectable sample rate in a time-synchronized manner on a group of input and/or output channels of an electronic circuit includes: configuring each channel of the group at a standard sample period; synchronously initiating all the channels of the group at the standard sample period; detecting an entry for a modified sample period TPeriod of a first channel of the group; detecting a current counter value TCounter; configuring the first channel at the modified sample period; establishing a waiting time of TWaiting clocks in accordance with TWaiting=TPeriod?mod(TCounter, TPeriod), where mod (TCounter, TPeriod) denotes the division remainder from the current counter value TCounter and the modified sample period TPeriod; and initiating the first channel after the waiting time TWaiting.Type: GrantFiled: March 26, 2021Date of Patent: October 22, 2024Assignee: DSPACE GMBHInventors: Dominik Lubeley, Marc Schlenger, Paul Gruber
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Patent number: 12119812Abstract: An electronic circuit for uniform distribution of a current includes: a first MOSFET and a second MOSFET, wherein the first MOSFET and the second MOSFET are connected in parallel in order to distribute a current applied to an input terminal, the current flowing towards an output terminal of the electronic circuit, wherein the input terminal is respectively connected to a drain terminal of the first MOSFET and to a drain terminal of the second MOSFET; and a terminal for a control voltage, wherein the control voltage is applied to a gate terminal of the first MOSFET and to a gate terminal of the second MOSFET. The first MOSFET comprises a first resistor at the gate terminal of the first MOSFET, and the second MOSFET comprises a second resistor at the gate terminal of the second MOSFET.Type: GrantFiled: December 14, 2022Date of Patent: October 15, 2024Assignee: DSPACE GMBHInventor: Paul Gruber
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Publication number: 20240329201Abstract: A simulator for the simulation of a distance for sensors (radar, LIDAR). The simulator includes a receiver, which is set up to receive a first sensor signal from the sensors (radar, LIDAR) and convert it into a work signal. A delay section with a plurality of delay lines is applied to at least one substrate. A first electrical switching device, which is set up to switch a first selection of delay lines as a function of a first selection signal in such a way that a signal path for the work signal includes the first selection. A transmitter is set up to convert the work signal into a second sensor signal after running through the signal path and send it to the sensors (radar, LIDAR). A method for operating the simulator and a delay section for the simulator are also provided.Type: ApplicationFiled: March 29, 2024Publication date: October 3, 2024Applicant: dSPACE GmbHInventor: Andreas HIMMLER
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Publication number: 20240303386Abstract: A computer-implemented method and system for the criteria-based creation of a scenarios library having virtual vehicle environments, for testing highly automated driving functions of a motor vehicle. Using predetermined criteria, a first scenario data set is determined representing a driving situation of interest and comprised by the sensor data. The first scenario data set, representing the driving situation of interest, is compared with second scenario data sets included in the scenarios library. A computer-implemented method for validating a model quality of a simulation model for performing a highly automated driving function of a motor vehicle is also provided.Type: ApplicationFiled: March 6, 2024Publication date: September 12, 2024Applicant: dSPACE GmbHInventors: Hagen HAUPT, Thorsten PUESCHL, Jann-Eve STAVESAND
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Publication number: 20240296112Abstract: A computer-implemented method to test an execution of at least one control unit function of a control unit via at least one computing unit of a simulation environment on a simulator. The control unit function is executed with a zero-time assumption of a discretely advancing simulation time between successive simulation steps in an event-oriented discrete simulation on the simulator. A cause of deadlock situations in the simulation are identified in that an observation service operated on the simulator compares the advance of the discrete simulation time with the advance of a simulator real time and, if the advance of the simulator real time beyond the advance of the discrete simulation time exceeds a predetermined limit value, at least indirectly creates stack traces of the at least one computing unit.Type: ApplicationFiled: March 1, 2024Publication date: September 5, 2024Applicant: dSPACE GmbHInventors: Stephan SCHEDLER, Stjepan POLJAK
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Patent number: 12079601Abstract: A computer-implemented method for creating a hierarchical block diagram in a graphical development environment includes: automatically creating a hierarchical black box for a respective further subsystem block. The hierarchical black box is configured to resolve a corresponding hierarchical level when selected by a user. The automatic creation is carried out via a callback function. The hierarchical black box has the following features: at least one interface description and/or graphical representation of the inputs/outputs of the respective further subsystem block in its hierarchical level, which the respective further subsystem block previously also occupied; at least one reference to model content for the respective further subsystem block, comprising further black boxes for the further subsystem blocks in the subordinate hierarchical levels; parameters that the respective further subsystem block previously also had; and generated source code of the respective further subsystem block.Type: GrantFiled: December 15, 2022Date of Patent: September 3, 2024Assignee: DSPACE GMBHInventors: Heiko Kalte, Dominik Lubeley