Abstract: A system and method for correcting connectivity errors in a mask layout are disclosed. The method includes comparing a first connection in a mask layout file to a second connection in a schematic netlist. A connectivity error is identified if the first connection does not match the second connection and the identified connectivity error is automatically corrected in the mask layout file.

Abstract: A photomask and method for eliminating design rule violations from the photomask are disclosed. A photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by comparing a feature dimension in a mask layout file with a design rule in a technology file, identifying a design rule violation if the feature dimension is less than the design rule and automatically correcting the identified design rule violation in the mask layout file.

Abstract: A system and method for correcting design rule violations in a mask layout file are disclosed. The method includes comparing a feature dimension in a mask layout file with a design rule in a technology file. If the feature dimension is less than the design rule, a design rule violation is identified and automatically corrected in the mask layout file.

Abstract: A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.

Abstract: A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.

Abstract: A method for correcting pattern errors on a photomask is disclosed. The method includes determining a proximity effect caused by a first feature on a second feature in a pattern data file. The total line edge length is calculated for the first feature and a dimension of the second feature is modified based on the total line edge length calculated or the first feature.

Abstract: A test wafer and method for investigating electrostatic discharge induced wafer defects are disclosed. The test wafer includes an electrostatic discharge (ESD) sensitive risk scale geometry, formed thereon. After exposure to a semiconductor manufacturing procedure, the test wafer may be analyzed by using the ESD risk scale geometry to identify and evaluate severity of any ESD effects associated with the semiconductor manufacturing procedure.

Abstract: A method and apparatus for monitoring and evaluating effects of electrostatic discharge associated with semiconductor manufacturing are disclosed. The method may include, for example, exposing a test photomask that contains an ESD sensitive geometry to a single or a variety of semiconductor manufacturing procedures. The test photomask may be analyzed to determine how much, if any, degradation of its geometry has occurred as a result of the exposure.

Abstract: A method and apparatus for monitoring and evaluating effects of electrostatic discharge associated with semiconductor manufacturing are disclosed. The method may include, for example, exposing a test photomask that contains an ESD sensitive geometry to a single or a variety of semiconductor manufacturing procedures. The test photomask may be analyzed to determine how much, if any, degradation of its geometry has occurred as a result of the exposure.

Abstract: The approach taken to provide variable writing speeds consists of the following: (1) Software in the Job Control subsystem that Identifies the minimum and maximum valid writing speeds, given the resist sensitivity, maximum beam current density, and requested write address size. if the variable writing speed option is enabled, Job Control selects the maximum valid speed. (2) Software in the Pattern Data Conversion subsystem that determines the number of stripes of pattern figure data to combine into each output bitmap for the selected writing speed. (3) Hardware in the Timing Logic Board to clock bitmap data to the serializer at the desired frequency.

Abstract: A dust cover having a film with an inorganic, anti-reflective coating and method for use during semiconductor fabrication. The dust cover is primarily for use during photolithography. The dust cover may include an amorphous fluoropolymer film having an inorganic, anti-reflective coating attached to a frame. The inorganic, anti-reflective coating preferably has a refractive index below 1.4.

Abstract: An electron beam blanking method and system for selectively interrupting the flow of electrons during an electron beam lithographic process minimizes electron beam movement during blanking as the electron beam reaches a target lithographic mask. A first deflection plate pair deflects electrons flowing in the electron beam in the direction of the target lithographic mask. The first deflection plate pair includes a first tapered gap that is formed so that electrons which enter the first tapered gap before the initialization of a blanking voltage experience progressively greater electric field as they pass through the plates for controlling the cumulative deflection as the electrons travel through the first deflection plate pair.

Abstract: A pattern mask pellicle comprising a peripheral frame, a transparent film extending across the top peripheral surface of the frame, and a peripheral gasket adhered to the bottom peripheral surface of the frame, the frame/gasket assembly including at least one tacky, continuous, tortuous path connecting an opening in the interior wall of the assembly with an opening in the exterior wall of the assembly. At least one pellicle is mounted on a pattern mask substrate to protect the pattern area during imaging in the production of integrated circuits.

Abstract: A method and apparatus are disclosed for removing a pellicle frame (52) from a photomask plate (50) where the pellicle frame (52) is adhered to a surface of the photomask plate (50) by an adhesive material (54). Tension is applied to the adhesive material (54) by applying force to separate the pellicle frame (52) and the photomask plate (50). A second surface of the photomask plate (50), opposite from the surface to which the pellicle frame (52) is adhered, is heated to raise the temperature of the adhesive material (54) and to raise the temperature of the photomask plate (50) greater than the temperature of the pellicle frame (52). The tension on the adhesive material (54) is then maintained until the adhesive material (54) releases the pellicle frame (52) from the photomask plate (50).