Abstract: A semiconductor device including a peripheral circuit structure, a cell structure including gate electrodes and stacked on the peripheral circuit structure, the cell structure including a cell region, a connection region, and a peripheral circuit connection region, the cell structure, a plurality of channel structures extending in a vertical direction through the gate electrodes in the cell region, each of the plurality of channel structures including a first end portion close to the peripheral circuit structure and a second end portion opposite to the first end portion, and a common source layer connected to the second end portion of each of the channel structures in the cell region may be provided.

Abstract: An object detection method and an object detection apparatus for detecting an object based on multi-features are provided. The object detection method includes: obtaining first-sensor data from a first sensor and obtaining second-sensor data from a second sensor, wherein the first sensor is a different type of sensor than the second sensor; extracting a first feature from the first-sensor data and extracting a second feature from the second-sensor data; determining a target feature-type by inputting the first and second features to a feature-type selection model which, based thereon, predicts the target feature-type; determining a target feature to be used for object detection according to the determined target feature-type; and determining an object detection result based on the determined target feature.

Abstract: A semiconductor device includes a substrate; an active pattern extending on the substrate in a first direction; a plurality of channel layers on the active pattern; a gate structure surrounding the plurality of channel layers, and extending in a second direction that intersects the first direction; blocking insulating layers on both side surfaces of the gate structure, respectively, each of the blocking insulating layers having an upper region having a first thickness and a lower region having a second thickness smaller than the first thickness; source/drain patterns on portions of the active pattern on both sides of the gate structure, the source/drain patterns defining trenches therein; contact structures on the source/drain patterns and filling the trenches; and a metal-semiconductor compound layer between the source/drain patterns and the contact structures.

Abstract: Disclosed is a multi-level defect detection method and system for detecting one or more defects in semiconductor wafers, including forming, among input images of the semiconductor wafers, a first image set of input images in which defects were not detected and a second image set of input images in which defects were detected; extracting image parameters from the first image set and determining whether the first image set can be enhanced; generating an image enhancement profile for the first image set and modifying the first image set based on the image enhancement profile and detecting one or more defects in the modified image set by performing a defect detection process thereon.

Abstract: A memory device includes a memory cell array including a plurality of memory cells, respectively connected to a plurality of bitlines, a first multiplexer including a plurality of transistors connected to the plurality of bitlines, a reference circuit that generates reference current, a decoding circuit that transmits the reference current to the first multiplexer, and a control logic circuit connected to the reference circuit and the decoding circuit. The control logic circuit controls control the decoding circuit to apply the reference current to transistors, connected to each of at least two bitlines, such that predetermined first current flows through the at least two bitlines.

Abstract: A washing machine may include: a hardness component remover including a resin charging chamber between a downstream buffer space and an upstream buffer space and containing an ion-exchange resin; a saturated regeneration water generation vessel in which saturated regeneration water is to be generated; a regeneration water passage connecting the saturated regeneration water generation vessel to the downstream buffer space; a drain passage connecting the upstream buffer space to a drain; a first on-off valve to open and close the regeneration water passage; a second on-off valve to open and close the drain passage; at least one processor; and memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform a regeneration process to regenerate the ion-exchange resin.

Abstract: A user equipment (UE) supporting a first radio access technology (RAT) network and a second RAT network, the UE includes processing circuitry configured to monitor whether a position of the UE has changed from a first position to obtain a monitoring result, a network connected to the UE switching from the first RAT network to the second RAT network based on the UE moving to the first position, and perform a re-connection operation to the first RAT network based on the monitoring result.

Abstract: A method and apparatus with a feature-level ensemble model are provided. A method of operating an ensemble model based on feature-level consolidation includes: obtaining queries by inputting a same input data item to respective transformer models, the transformer models generating respective queries from the input data item; forming an ensemble query corresponding to the queries; and generating a predicted value of the input data item by applying the ensemble query to a prediction model that includes a transformer decoder, the prediction model inferring the predicted value from the ensemble query.

Abstract: A high bandwidth memory includes a base die and a memory stack on the base die. The memory stack includes a plurality of memory dies. The memory stack includes a first memory die closest to the base die among the plurality of memory dies and having a first width in a horizontal direction, and a second memory die on the first memory die and having a second width in the horizontal direction, the first width is smaller than the second width.

Abstract: A semiconductor device includes a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction crossing the first direction; a plurality of memory cells in a plurality of areas in which the plurality of word lines and the plurality of bit lines intersect; and a semiconductor element connected to at least one of the plurality of word lines and the plurality of bit lines, the semiconductor element including a first active pattern and a second active pattern overlapping the first active pattern along a height direction perpendicular to the first and second directions.

Abstract: A gas supply system includes a loading/unloading stage including a cradle loader where a cradle loaded with a gas container is loaded, a test buffer chamber is configured to test the gas container, and a loading/unloading robot configured to transfer the gas container between the cradle and the test buffer chamber. A gas supply stage includes a storage queue configured to temporarily store the gas container, a gas supply cabinet where the gas container is mounted, and a transfer robot configured to transfer the gas container between the test buffer chamber and the storage queue and between the storage queue and the gas supply cabinet.

Abstract: A gas supply system includes a loading/unloading stage including a cradle loader where a cradle loaded with a gas container is loaded, a test buffer chamber is configured to test the gas container, and a loading/unloading robot configured to transfer the gas container between the cradle and the test buffer chamber. A gas supply stage includes a storage queue configured to temporarily store the gas container, a gas supply cabinet where the gas container is mounted, and a transfer robot configured to transfer the gas container between the test buffer chamber and the storage queue and between the storage queue and the gas supply cabinet.

Abstract: A training method for similarity measurement and a measuring apparatus for similarity measurement and operating method thereof are provided. A method, performed by a computing device, includes: based on a first training parameter, embedding vectors of first processes included in a first process-sequence and embedding vectors of second processes included in a second process-sequence, respectively; based on a second training parameter, mapping first embedding vectors respectively corresponding to the first processes to second embedding vectors respectively corresponding to the second processes; and based on a result of the mapping, determining a similarity score indicating a similarity between the first process-sequence and the second process-sequence.

Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.

Abstract: A semiconductor device including a gate stacking structure, a plurality of channel structures, and a separation pattern. The plurality of channel structures including an adjacent channel structure including a first portion having a surface adjacent to the separation pattern and a separation surface spaced apart from the separation pattern. At least one of the gate dielectric layer or the channel layer is on the separation surface and the adjacent surface in the first portion of the adjacent channel structure.

Abstract: A scrubber may include a plasma processing unit including a plasma generating device and a power generating device, a combustion processing unit including a combustor, which is used to form a flame, a connection conduit connected to the plasma processing unit and spaced apart from the combustion processing unit, and a back-end processing unit connected to the combustion processing unit. The connection conduit may be used to supply a waste gas to the plasma generating device, and the plasma generating device may be configured to form plasma using the waste gas. The plasma and combustion processing units may be configured to provide a first reaction space, in which the plasma is formed, and a second reaction space, in which the flame is formed.

Abstract: A display panel includes an array substrate, a plurality of light-emitting units arranged on the array substrate, an isolation structure arranged on the array substrate and separating the plurality of light-emitting units, and an encapsulation layer. The encapsulation layer includes at least a first encapsulation layer, each of the at least a first encapsulation layer is arranged on a side of a corresponding light-emitting unit of the plurality of light-emitting units away from the array substrate. An orthographic projection of the light-emitting unit on the array substrate is located within an orthographic projection of a corresponding first encapsulation layer on the array substrate. At least a part of the first encapsulation layer beyond the corresponding light-emitting unit is located between the corresponding light-emitting unit and the isolation structure.

Abstract: A gas supply system includes a loading/unloading stage including a cradle loader where a cradle loaded with a gas container is loaded, a test buffer chamber is configured to test the gas container, and a loading/unloading robot configured to transfer the gas container between the cradle and the test buffer chamber. A gas supply stage includes a storage queue configured to temporarily store the gas container, a gas supply cabinet where the gas container is mounted, and a transfer robot configured to transfer the gas container between the test buffer chamber and the storage queue and between the storage queue and the gas supply cabinet.

Abstract: Provided are a resist composition and a pattern formation method using the same. The resist composition may include an organometallic compound represented by one of Formulae 1-1 to 1-4, and an additive represented by Formula 2: wherein M11, L11 to L14, a11 to a14, R11 to R14, b11 to b14, Y11 to Y13, X11 to X13, Y21, Y22, L21, and a21 in Formulae 1-1 to 1-4 and 2 are described in the specification.

Abstract: Provided is a multi-layered ceramic capacitor in which a penetration-type electrode unit, which is manufactured in a cone shape, passes through a plurality of internal electrodes in a collective stack of the internal electrodes and the dielectric layers, so that the capacitor is miniaturized and the electrical reliability thereof is improved.