Abstract: A method measures the distance between a time-of-flight (ToF) sensor and an object based on cross time shift. The ToF sensor includes at least one depth pixel and a light source to direct transmission light to an object. The depth pixel may have a multi-tap structure and may generate sampled data based on reception light and demodulation signals having different phases. The reception light corresponds to the transmission light reflected from the object. The method includes generating time shifts between the transmission light and demodulation signals, performing sampling operations to generate the sampled data corresponding to the time shifts, determining a cross time shift based on sampled data of a first reference tap substantially equaling sampled data of a second reference tap, and determining the distance between the ToF sensor and the object based on the cross time shift.

Abstract: An electronic device and method are disclosed. The electronic device includes a display an extended screen area that is exposed or stowed, according to a change in a state of the display of the electronic device, communication circuitry configured to transceive a signal to or using an angle-of-arrival (AOA) antenna disposed within the extended screen area, a memory, and a processor. The processor implements the method, including: determining a position of the electronic device relative to an external electronic device, using the communication circuitry, executing a sharing operation with the external electronic device, identifying whether the display of the electronic device is disposed in a first state or a second state, based on detecting that the display is disposed in the first state, perform a first positioning operation for the external electronic device, and displaying a sharing interface according to the first positioning operation on the display.

Abstract: An apparatus and a method for outputting image data, and an electronic device are provided. The apparatus includes a first parameter setter, an image signal processor, and an encoder, wherein the first parameter setter sets a first configuration parameter for the image signal processor based on a complexity associated with an input image frame, wherein the image signal processor performs an image signal processing on at least one image frame to generate processed image data based on the first configuration parameter, wherein the encoder performs encoding processing on the processed image data to generate encoded image data. The apparatus and the method for outputting image data, and the electronic device of the present disclosure adjust parameters of the image signal processor and the encoder according to the complexity associated with an input image frame, thereby effectively improving the overall performance of image processing, encoding and compression.

Abstract: The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). A method is provided for allocating resources in the time domain, the method including in a downlink transmission part of a DL/UL-period of a frame allocating a preset number of adjacent OFDM-symbols for transmission of a PDCCH, generating a bundle of time intervals comprising an integer number of adjacent time intervals, wherein each time interval includes a preset number of OFDM-symbols, wherein the PDCCH relates to the entire bundle of time intervals, allocating a subbundle of OFDM-symbols to transmit a DMRS pattern which multiplexes DMRS signals for a required number of MIMO layers of a PDSCH, and allocating OFDM-symbols for transmission of the PDSCH.

Abstract: A method for operating a user equipment (UE) comprises receiving a configuration via a radio resource control (RRC) message, the configuration including information about a channel state information reference signal (CSI-RS) burst comprising B>1 time instances of CSI-RS transmission; measuring the CSI-RS burst; determining, based on the measurement, time-domain (TD) or Doppler domain (DD) components of a downlink (DL) channel; and transmitting a CSI report including an indication about the TD or DD components of the DL channel.

Abstract: A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

Abstract: A display apparatus may include: a camera; a display; a memory storing one or more instructions; and at least one processor configured to execute the one or more instructions stored in the memory to: analyze an image captured by the camera and detect a free space included in the image; determine an exercise motion performable in the free space, based on the detected free space; and control the display to output exercise content based on the determined exercise motion.

Abstract: A method includes capturing an image and associating the image with a camera pose for each of multiple cameras. The method also includes determining, for each camera, a first contribution of the image for a first virtual view for display on a first display and a second contribution of the image for a second virtual view for display on a second display. The method further includes determining, for each camera, a first confidence map for the first virtual view based on the camera pose and a position of the camera in relation to a first virtual camera and a second confidence map for the second virtual view based on the camera pose and the position of the camera in relation to a second virtual camera. In addition, the method includes generating the first virtual view by combining the first contribution using the first confidence map for each of the cameras and the second virtual view by combining the second contribution using the second confidence map for each of the cameras.

Abstract: A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.

Abstract: A semiconductor package may include a first package substrate; a power supply device electrically connected to a top surface of the first package substrate; a power management semiconductor chip electrically connected to the top surface of the first package substrate, wherein the power management semiconductor chip is horizontally apart from the power supply device; and a semiconductor device electrically connected to the top surface of the first package substrate, wherein the semiconductor device is horizontally apart from the power management semiconductor chip, wherein the semiconductor device includes: a second package substrate electrically connected to the top surface of the first package substrate; a semiconductor chip electrically connected to a top surface of the second package substrate; and a sub-battery electrically connected to the semiconductor chip through the second package substrate or directly connected to the semiconductor chip.

Abstract: A semiconductor memory device includes active regions arranged at a first vertical level on a substrate, a thickness of each active region in a vertical direction varying in a first lateral direction, a first word line surrounding first active regions belonging to a first group of the active regions, a second word line surrounding second active regions belonging to a second group of the active regions, the second word line being apart from the first word line in the first lateral direction, and a pair of word line pads being at the first vertical level on the substrate, the pair of word line pads being connected to the first word line and the second word line, respectively.

Abstract: A semiconductor device includes a peripheral circuit structure including a circuit substrate and circuits on the circuit substrate, and a through-electrode region overlapping the peripheral circuit structure in a vertical direction, wherein the through-electrode region includes an insulating structure including first insulating films and second insulating films, which include different materials from each other and are alternately stacked one-by-one in the vertical direction, and having an upper surface that has a varying height in the vertical direction along with each of a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, an interlayer dielectric covering the upper surface of the insulating structure, and through-electrodes passing through the insulating structure and the interlayer dielectric in the vertical direction in a local region of the through-electrode region and each configured to be connected to one circuit selected from the circuits of

Abstract: An image sensor includes a semiconductor substrate including a plurality of pixels and having a first surface and a second surface opposite to the first surface, the semiconductor substrate having a trench formed through the first surface and the second surface; a micro-lens on the second surface; an isolation layer in the trench that isolates the pixels from each other; and an etching barrier layer in the isolation layer and having a first depth from the first surface. The etching barrier layer has a corrosion resistance higher than a corrosion resistance of a region of the semiconductor substrate other than the etching barrier layer.

Abstract: A non-carbonyl metal deposition adjuvant may include at least one of Si, O, S, or N. A deposition method may include feeding the non-carbonyl metal deposition adjuvant to a channel hole where amorphous Si is deposited before feeding a late transition metal precursor into the channel hole where the amorphous Si is deposited. A semiconductor device may include a semiconductor structure defining the channel hole, where the semiconductor structure may include a metal layer including crystallized Si and a late transition metal and where the semiconductor structure may include a thin film surrounding the channel hole. The thin film may include oxide films and nitride films alternately disposed. Grains in the metal layer may include the crystallized silicon. The late transition metal may have an average diameter of greater than or equal to 50 nm.

Abstract: A data processing apparatus spaced apart from a host and configured to process data in a memory in conjunction with the host includes a near-memory processing unit configured to receive a command from the host, compress or decompress the data in response to the command, and manage an entry of the compressed data; and a buffer configured to store the data or the compressed data based on the entry.

Abstract: A memory module may include a module substrate including first substrate pads and an insertion portion that has a module power terminal on a first substrate side portion of the module substrate; at least one semiconductor device on the module substrate and including chip pads electrically connected to the first substrate pads; substrate wirings including a first power connection wiring that electrically connects the module power terminal and the at least one semiconductor device; test wirings including a power test wiring that is branched from the first power connection wiring and has an end portion exposed from a second substrate side portion, the second substrate side portion adjacent the first substrate side portion; and a short protection structure on the module substrate, the short protection structure being adjacent the second substrate side portion, in the power test wiring, and configured to selectively block electrical flow through the power test wiring.

Abstract: A semiconductor package may include a semiconductor die stack in a stepped pattern, an encapsulation layer sealing the semiconductor die stack and including a first surface coplanar with a bottommost surface of the semiconductor die stack and a second surface opposite the first surface, the second surface having a groove, a printed circuit board on the second surface of the encapsulation layer and including a conductive pad facing the second surface of the encapsulation layer, a conductive connector filling the groove, and a bonding wire group penetrating the conductive connector in a vertical direction and connecting the semiconductor die stack to the conductive pad of the printed circuit board. A width of the conductive connector in a lateral direction may be greater than or equal to a width of the conductive pad in the lateral direction.

Abstract: Provided is a method of operating an electronic device, the method including receiving data blank information from a serving cell, identifying at least one first subframe and at least one second subframe based on a timing offset and the data blank information, resource allocations between the serving cell and an interference cell overlapping in the at least one first subframe, and the resource allocations not overlapping in the at least one second subframe, increasing a first weight for a first log likelihood ratio (LLR) corresponding to the at least one first subframe, decreasing a second weight for a second LLR corresponding to the at least one second subframe, and calculating a third LLR based on the first LLR and the second LLR.

Abstract: The invention relates to an integral water-cooling radiator including a water cooling block. The water cooling block includes a fixed base, the fixed base is formed with a first flow chamber and a second flow chamber, and the fixed base is formed with a first inlet and a first outlet. A water cooling liquid flows into the first flow chamber, and under the drive of an impeller member, is discharged via the first outlet, such that the water cooling liquid forcibly carries away heat for dissipation. During dissipation, the water cooling liquid further flows through the second flow chamber. As compared with a single flow chamber, the increase of the flow regions causes a significant decrease in load of the impeller member. This prolongs the service life and increases the motor efficiency, so as to improve the pump efficiency, thus significantly improving the flow efficiency of the water cooling liquid.

Abstract: A semiconductor memory device may include a first word line surrounding first active regions and a second word line surrounding second active regions at a first vertical level on a substrate, and a pair of word line pads at the first vertical level. The first and second word lines may be apart from each other in a first lateral direction and may extend lengthwise in a second lateral direction. The first word line may be connected to a first word line pad in the pair of word line pads and the second word line may be connected to a second line pad in the pair of word line pads. In a view from above at the first vertical level, the first and second word lines may be offset from each other the second lateral direction.