Patents Assigned to Electronics Co., Ltd.
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Publication number: 20250246573Abstract: A semiconductor package includes a package substrate including substrate pads on an upper portion of the package substrate, a first semiconductor chip on the package substrate, a first chip pad on the first semiconductor chip, a first conductive connection pattern on an upper surface of the first chip pad, an upper surface of the first semiconductor chip, and an upper surface of a first substrate pad among the substrate pads, and a first insulation layer on the package substrate and covering the first semiconductor chip, the first chip pad and the first conductive connection pattern.Type: ApplicationFiled: December 26, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Wonil SEO, Kwangyong LEE, Jiwon SHIN, Sanghyeon LEE
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Publication number: 20250245354Abstract: An electronic system comprising a storage device configured to generate a device public key and a device private key based on a device CDI generated from a device DICE, generate a host certificate including a first device signature generated by signing a host public key with the device private key in response to receiving a request of generating the host certificate including the host public key, and send a request of generating a device certificate including the host certificate and the device public key; and a host device configured to generate the host public key and a host private key based on a host CDI generated by a host DICE, generate the device certificate including a first host signature generated by signing the device public key with the host private key in response to the request of generating the device certificate, and send the device certificate to the storage device.Type: ApplicationFiled: July 11, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Seung-Ho LEE, Yun-Ho YOUM, Myung-Sik CHOI
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Publication number: 20250248117Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.Type: ApplicationFiled: April 21, 2025Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Keun Hwi CHO, Sangdeok KWON, Dae Sin KIM, Dongwon KIM, Yonghee PARK, Hagju CHO
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Publication number: 20250248157Abstract: An image sensor that includes a substrate region including first and second pixel regions; and a microlens array layer on the substrate region and including a first microlens and a second microlens respectively corresponding to the first and second pixel regions. The first pixel region and the second pixel region are respectively adjacent to a center and an edge of the microlens array layer. The first microlens is offset from the first pixel region and has a first inclination. The second microlens is offset from the second pixel region and has a second inclination greater than the first inclination. A degree to which the first and second microlenses are offset from the first and second pixel regions, and the first and second inclinations are based on an incident angle of incident light to the first and second microlenses.Type: ApplicationFiled: August 30, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventor: Mintae CHUNG
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Publication number: 20250248198Abstract: The disclosure provides a display panel and a display device. The display panel includes a display substrate and a lens structure. The display substrate includes a plurality of light-emitting devices and a receiving layer located on light-emitting sides of the light-emitting devices. The lens structure is located on the receiving layer and includes a plurality of lens units, and the lens units are arranged in correspondence with the light-emitting devices. Each of the lens units includes a color blocking layer configured to absorb light in ambient light that is different in color from light emitted from a corresponding light-emitting device. The lens unit has a refractive index greater than a refractive index of the receiving layer.Type: ApplicationFiled: April 21, 2025Publication date: July 31, 2025Applicant: KunShan Go-Visionox Opto-Electronics Co., Ltd.Inventors: Junlin HU, Wentao YING, Rubo XING, Yiming JIA, Xiaokang ZHOU, Yanhua CHENG, Xingxing YANG
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Publication number: 20250247763Abstract: Provided is an operation method of user equipment, the operation method including transmitting a first message including assistance information to a serving cell based on a determination, the assistance information corresponding to a conditional handover, receiving a conditional handover-related message indicating adjusted first conditions, the adjusted first conditions having been adjusted from first conditions based on the assistance information, and the first conditions being conditions for performing a conditional handover, evaluating the adjusted first conditions to obtain an evaluation result, and performing the conditional handover with a target cell based on the evaluation result.Type: ApplicationFiled: January 13, 2025Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventor: Yangsoo KWON
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Publication number: 20250246926Abstract: A method includes: acquiring information indicating first magnitude of first power supplied from a first power source and information indicating second magnitude of second power supplied from a second power source; comparing the first magnitude of the first power and the second magnitude of the second power; comparing the second magnitude of the second power and magnitude of a sum of multiple power values when the second magnitude of the second power is changed to be equal to the first magnitude of the first power based on determining that the first magnitude of the first power is smaller than the second magnitude of the second power; controlling the second magnitude of the second power to be equal to the first magnitude of the first power based on identifying that the second magnitude of the second power is smaller than the magnitude of the sum of multiple power values.Type: ApplicationFiled: December 18, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventor: Sangju KIM
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Publication number: 20250248038Abstract: A semiconductor memory device includes a substrate including first and second regions; a first stacked structure on the first region, and having first gate electrode layers and first insulating layers alternately stacked; a second stacked structure on the first stacked structure, and having second gate electrode layers and second insulating layers alternately stacked; an oxide structure on the second region; a first mold structure on the oxide structure, and having nitride and oxide layers alternately stacked; a channel structure penetrating the first and second stacked structures in the first region; and a through structure penetrating the oxide structure and the first mold structure in the second region. The oxide structure and first stacked structure are at a same level, and the first mold structure and second stacked structure are at a same level.Type: ApplicationFiled: August 23, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Hong Seok CHOI, Ok Kyu LEE, Jin Yeol YANG
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Publication number: 20250248084Abstract: A semiconductor device may include an active pattern on an active region of a substrate, a channel pattern on the active pattern and including first, second, and third semiconductor patterns that are stacked to be spaced apart from each other, a gate electrode on the channel pattern, and a gate dielectric layer between the channel pattern and the gate electrode. The gate dielectric layer may include an interface layer, and first, second, and third high-k dielectric layers that are sequentially stacked on the interface layer. The first high-k dielectric layer may include a first dipole element, and the second high-k dielectric layer may include a second dipole element.Type: ApplicationFiled: July 2, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Inhyun SONG, Jongsu KIM, Myung Gil KANG, Ohseong KWON, Junggil YANG, Inho YEO, Eunguk CHUNG
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Publication number: 20250241422Abstract: The present disclosure relates to hair styling equipment technologies, in particular to a hair styling device, which includes two clamping plates and a handle connected with the two clamping plates. Each clamping plate includes a shell, a heating plate, and at least one connecting structure connected between the shell and the heating plate. A heat insulation gap is defined between the shell and the heating plate. The heat insulation gap is capable of being reduced along with movement of the heating plates relative to the shells. The hair styling device uses air as the insulation material due to the heat insulation gap, which greatly reduces the heat transmitted from the heating plate to the shell. The height of the insulation gap can be reduced along with movement of the heating plate, which can better clamp the hair and provide users with a better hair styling experience.Type: ApplicationFiled: April 21, 2025Publication date: July 31, 2025Applicant: Shenzhen Yangwo Electronic Co., Ltd.Inventor: Dejin DUAN
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Publication number: 20250244888Abstract: A semiconductor device may include a memory configured to store data, a controller configured to monitor input/output data of the memory, and upon receiving a computing command and an address information from a host, determine computing on first data among the input/output data based on the computing command and the address information, and a computing engine configured to perform computing on the first data in response to the determining of the controller, where the address information instructs an address of the memory by using a physical region page (PRP) or a scatter gather list (SGL).Type: ApplicationFiled: June 25, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Jongwon LEE, Jungmin SEO, Hong Rak SON
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Publication number: 20250244900Abstract: A method for data deduplication of a storage apparatus and the storage apparatus are provided. In particular, a method for data deduplication of a storage apparatus, wherein the storage apparatus comprises a storage class memory (SCM) and a flash memory, the method comprising: obtaining a search result of searching for a fingerprint in fingerprint data stored in the SCM the fingerprint generated based on written data; and writing the written data to the flash memory in the case that the search result is the fingerprint generated based on the written data is not present in the fingerprint data.Type: ApplicationFiled: April 24, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Kun ZHANG, Hao YAN
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Publication number: 20250245288Abstract: A matrix multiplier includes an input vector scaler configured to generate a scaled input matrix based on a first input matrix and a plurality of scale factors, a first data type converter configured to convert the data type of the scaled input matrix to fixed-point and generate a fixed-point input matrix, a multiplication and accumulation operator array configured to receive the fixed-point input matrix and a plurality of binary vectors, generate a fixed-point output matrix based on the fixed-point input matrix and the plurality of binary vectors, generate the first input matrix and the second input matrix, and generate a first output matrix based on the first input matrix and the second input matrix, and a second data type converter configured to convert the data type of the fixed-point output matrix to a floating point and generate a second output matrix.Type: ApplicationFiled: October 16, 2024Publication date: July 31, 2025Applicants: Samsung Electronics Co., Ltd., NAVER CORPORATIONInventors: Suchang KIM, Jae Hun JANG, Younho JEON, Yeo-Reum PARK, Jihoon LIM, Hong Rak SON, Se Jung KWON, Byeoung Wook KIM, Baeseong PARK, Dongsoo LEE
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Publication number: 20250245403Abstract: A method for predicting quality of a workpiece includes: obtaining optical emission spectroscopy (OES) raw data of the workpiece, the OES raw data having a time dimension and a wavelength dimension; selecting, in the wavelength dimension, a first portion of the OES raw data that falls within wavelength ranges selected based on a material used in a process of producing the workpiece; selecting, in the time dimension, a second port of the OES raw data that falls within a time range corresponding to a specific step of the process, where the specific step is to be analyzed; generating tokens by grouping the selected portions of the OES raw data; and training a model with the tokens.Type: ApplicationFiled: January 31, 2025Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Deokwon SIM, Sangwon BAEK, Kaeweon YOU, Hyunsoo LEE, Byungyong CHOI, Jonghyun KIM, Jongik HONG
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Publication number: 20250244681Abstract: Provided are an electronic device and a method of an operation thereof. The electronic device includes a memory and processing circuitry configured to execute the instructions stored in the memory to cause the electronic device to acquire a first input image based on an image of a design pattern to be formed on a wafer, transform the first input image into a second input image based on a factor not affecting a process of manufacturing a semiconductor device, and train a process simulation model by using a pair of the first input image and the second input image.Type: ApplicationFiled: December 4, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Chulho JUNG, Jaewon YANG, Jungmin KIM, Sang Chul YEO, Hyeok LEE
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Publication number: 20250244875Abstract: An electronic device with data processing includes one or more processors configured to in response to receiving a checkpoint signal, determine a location of related data of an application in a memory region, based on the location of the related data in the memory region, perform a checkpointing operation on the related data using either one or both of a host processor and an accelerator processor, and compress the related data using the either one or both of the host processor and the accelerator processor that has performed the checkpointing operation, wherein the location of the related data in the memory region comprises a location in either one or both of a host memory region and an accelerator memory region.Type: ApplicationFiled: January 13, 2025Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Tian LIU, Junyeon LEE, Xing BIAO, Byungwoo BANG, Huiru DENG, Fengtao XIE
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Publication number: 20250246251Abstract: Provided is a memory device with a vertical channel structure. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.Type: ApplicationFiled: April 18, 2025Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Yongsung CHO, Minjae SEO, Kyoman KANG, Byungsoo KIM
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Publication number: 20250247084Abstract: A method of operating a memory device includes receiving a quadrature clock and performing quadrature error correction of the quadrature clock in a non-sequential scheme, wherein the quadrature clock includes a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase.Type: ApplicationFiled: June 26, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventor: Yoonjae CHOI
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Publication number: 20250246476Abstract: In a method of manufacturing a semiconductor package, a wafer having a first surface and a second surface may be provided; a protective tape for wafer grinding process may be attached on the first surface of the wafer; the wafer having the protective tape attached thereon may be provided on a support member; the second surface of the wafer may be grinded; and the protective tape for wafer grinding process may include a first PSA layer attached on the first surface of a wafer, the first PSA layer having a first elastic modulus, a second PSA layer on the first pressure sensitive layer, the second PSA layer having a second elastic modulus greater than the first elastic modulus, and a plurality of outer layers provided between the support member and the second PSA layer.Type: ApplicationFiled: January 22, 2025Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Yeonsu SONG, Sangil CHOI
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Publication number: 20250248102Abstract: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device includes etching a stack structure to form a first trench on a first side of a dummy gate on a stack structure a second trench on a second side of the dummy gate opposite to the first side of the dummy gate, wherein the second semiconductor layer that remain after the formation of the first and second trenches form a plurality of nanosheets, partially etching the first and second trenches to form a third trench a fourth trench, forming a first sacrificial pattern inside the fourth trench, and forming a first source/drain region inside the third trench and a second source/drain region on the top surface of the first sacrificial pattern inside the fourth trench.Type: ApplicationFiled: July 17, 2024Publication date: July 31, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Young Dae CHO, Hyo Jin KIM, Yong Jun NAM, Tae Hyung LEE, Sung Keun LIM, In Geon HWANG
